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Lect6 .pdf

Original filename: Lect6.pdf
Title: Lecture 6
Author: naharte

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Lecture 6


2’s complement
• Recall how to represent negative numbers in
binary? (2E6)
• 2’s complement makes addition and subtraction
seamless for hardware
• To convert to 2’s complement (quick way), invert
all bits and add 1 to LSB
• Addition
– add normally, discard any carry out from sign bit

• Subtraction
– Convert subtrahend to 2’s complement and then add,
again discard any carry out from sign bit position
3C7 Digital Systems Design


Half Adder & Full Adder
• Half Adder
– inputs A, B
– outputs Carry, Sum

• Full Adder
– inputs A, B, Carry-in
– outputs Sum, Carry-out

S = Ci ⊕ A ⊕ B
Co = BCi + ACi + AB
– Cascade to make multiple-bit adder
3C7 Digital Systems Design


4-Bit Ripple-Carry Adder

3C7 Digital Systems Design


Overflow for 2C addition
• Output of arithmetic
operation exceeds
• In unsigned binary
addition, just check Co of
MSB full adder
• More complicated in 2C!
• Think:

A = an−1an−2an−3 La1a0

+ B = bn−1bn−2bn−3 Lb1b0
Sum = sn−1sn−2sn−3 Ls1s0

V = an −1bn −1 sn −1 + an −1 bn −1sn −1

– A and B have to have
same sign for overflow
– Sign of sum different to A
and B for overflow
– Check these three
3C7 Digital Systems Design


Overflow ctd
• An alternative:

V = con −1 ⊕ con − 2

• XOR the carry-in and carry-out of MSB adder
• Scenario: Carry in 0, carry out 1
– only way to get carry-out 1 is if an-1 and bn-1 are both 1
(negative numbers). Gives sum 0 and carry out 1 i.e.
– Added two negative numbers, got positive result

• Scenario 2: Carry in 1, carry out 0
– Since you have carry-in of 1, both an-1 and bn-1 must be
0 to give no carry out. Hence sum is 1.
– Added two positive numbers and got negative result
3C7 Digital Systems Design


4-bit Adder/Subtractor

3C7 Digital Systems Design


Carry Lookahead Circuit
• Ripple adder requires propagation of carry
bits from previous stage
– Delay, increases with number of bits

• Carry Lookahead logic
– express each ci in terms of ai ai −1 L a0 and

bi bi −1 L b0 and co

3C7 Digital Systems Design



Carry Lookahead
• Define functions carry generate and carry

Generate : Gi = ai bi
Propagate : Pi = ai ⊕ bi
• Recall expression for carry out
couti = Gi + Pi cini

si = Pi ⊕ cini
3C7 Digital Systems Design


Carry Lookahead
• Carry out logic can
be rewritten
• Refer to Katz
• i-th carry signal is
OR of i+1 product
terms with up to
i+1 literals
• 3 gate delays
– One for the
generate and
– one to AND these
– one to OR all
product terms
3C7 Digital Systems Design

cout0 = G0 + P0cin0
cout1 = G1 + P1G0 + P1P0cin0
cout2 = G2 + P2G1 + P2P1G0 + P2P1P0cin0
cout3 = G3 + P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1P0cin0


Logic for 4-bit Carry Lookahead
2 gate delays for each term

3C7 Digital Systems Design


Overall delay in carry lookahead

3C7 Digital Systems Design


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