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271 TEST 9 SHORT .pdf


Original filename: 271 TEST 9 SHORT.pdf
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NAME

_

DATE

_

Shift Registers
TEST: SHIFT REGISTERS
Answer the questions in the space provided.
1. The unit shown in Fig. 9-1 is a
load shift register.
a. Broadside
b. Multibit
c. Parallel
d. Serial
2. The shift register shown in Fig. 9-1 is best described as a 4-bit
_____________
-type unit.
a. Shift-left nonrecirculating
b. Shift-left recirculating
c. Shift-right nonrecirculating
d. Shift-right recirculating
3. Refer to Fig. 9-1. The logic states appearing at the output indicators
after pulse t1 are
. [4 bits, with bit A on the left and bit
D on the right]
4. Refer to Fig. 9-1. The logic states appearing at the output indicators
after pulse 12 are
. [4 bits, with bit A on the left and bit
D on the light]
5. Refer to Fig. 9-1. The logic states appearing at the output indicators
after pulse t3 are
. [4 bits, with bit A on the left and bit
D on the right]

1.

_

2.

_

3.

_

4.

_

5.

_

OUTPUT indicators

o

0

~

Data input
Q

D

eLK
eLR

eLR

eLR

eLR

~CIOCk

----.....

Clear

o

flip-flops = 7474 TIL

les

I
6. Refer to Fig. 9-1. The logic states appearing at the output indicators
after pulse t4 are
. [4 bits, with bit A on the left and bit
D on the right]
7. Refer to Fig. 9-1. The logic states appearing at the output indicators
after pulse t5 are
. [4 bits, with bit A on the left and bit
D on the right]
8. Refer to Fig. 9-1. The logic states appearing at the output indicators
after pulse t6 are
. [4 bits, with bit A on the left and bit
D on the right)
9. The shift register shown in Fig. 9-2 is best described as a 3-bit
______
-type unit.
a. Shift-left nonrecirculating
b. Shift-left recirculating
c. Shift-right nonrecirculating
d. Shift-right recirculating

6.

_

7.

_

8.

_

9.

_

OUTPUT indicators
A

~-~

C

C

---Jo-

___

8

-+-_---,

....,:8=--A

Parallel load
data inputs

---,

,---I----+--+--+---j---,
l-- .•...•
rJ J

P$

Q 1---'[1

CLK

CLK
l---+---4 K

~~C~IO~c~k_~
~r----~~C~le~a~r

+-_~~
~

CLR

Q 1--+--4

__-+__~
~

-J

J-K flip-flops;

7476 ICs

Fig. 9-2 Pulse-train problem.

10. Refer to Fig. 9-2.
after pulse t1 are
C on the right]
11. Refer to Fig. 9-2.
after pulse t2 are
C on the right]
12. Refer to Fig. 9-2.
after pulse t3 are
C on the right]
13. Refer to Fig. 9-2.
after pulse t4 are
C on the right)
14. Refer to Fig. 9-2.
after pulse t5 are
C on the right]
15. Refer to Fig. 9-2.
after pulse t6 are

The logic states appearing at the output indicators
. [3 bits, with bit A on the left and bit

10.

_

The logic states appearing at the output indicators
. [3 bits, with bit A on the left and bit

11.

_

The logic states appearing at the output indicators
. [3 bits, with bit A on the left and bit

12.

_

The logic states appearing at the output indicators
. [3 bits, with bit A on the left and bit

13.

_

The logic states appearing at the output indicators
. [3 bits, with bit A on the left and bit

14.

_

The logic states appearing at the output indicators
_[3 bits, with bit A on the left and bit

15.

_

r
NAME

_

DATE

16. Refer to Fig. 9-2. The logic states appearing at the output indicators
after pulse t7 are
. [3 bits, with bit A on the left and bit
C on the right]
17. Refer to Fig. 9-2. The logic states appearing at the output indicators
after pulse t8 are
. [3 bits, with bit A on the left and bit
C on the right]
18. The unit shown in Fig. 9-2 is a(n)
load shift register.
a. Auto
b. Parallel
c. Serial
d. Synchronous
19. Refer to Fig. 9-3. The shift-left operation is accomplished with the 74194
K' when So is
(IDGH, LOW), Sj is HIGH, and the clock
pulse goes from LOW to HIGH.

_

16.

_

17.

_

18.

_

19.

_

OUTPUT indicators
Mode control
Parallel load

So = 1, 5, = 1

Shift right

So = 1, 5, = 0
So = 0,5, = 1
So = 0,5, = 0

Shift left
Inhibit

"0"
"1"

B

111"

C

0"

D

If

o
0
0
_=--_-=-_..::-....i
o

o

o

r-:I

~

o

1

•••

OA
081---...J
Oc 1-------1

Shift right
---~--I
serial input
__

Shift left

__

serial input
Clock

____________________

°D~---------~
Universal
shift
register
(74194)

Clear

~-

--

--LJ

Parallel
load inputs _---A

o

~-=------aL_..,....-_ .•.....
.J

-

Mode controls

---------~
5,

Fig. 9-3 Pulse-train problem.

20. Refer to Fig. 9-3.
after pulse tl are
D on the right]
21. Refer to Fig. 9-3.
after pulse t2 are
D on the right]
22. Refer to Fig. 9-3.
after pulse t3 are
D on the right]
23. Refer to Fig. 9-3.
after pulse t4 are
D on the right]
24. Refer to Fig. 9-3.
after pulse t5 are

The logic states appearing at the output indicators
. [4 bits, with bit A on the left and bit

20.

_

The logic states appearing at the output indicators
. [4 bits, with bit A on the left and bit

21.

_

The logic states appearing at the output indicators
. [4 bits, with bit A on the left and bit

22.

_

The logic states appearing at the output indicators
. [4 bits, with bit A on the left and bit

23.

_

The logic states appearing at the output indicators
. [4 bits, with bit A on the left and bit

24.

_


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