Report (PDF)

University of California Santa Barbara
Department of Electrical and Computer Engineering
Academic Year 2012–2013
Fall Quarter

ECE220A Semiconductor Device Processing

Fabrication of NMOS Transistors
Group 7:
Merve Albayrak
Andreas De Groote
Gary Fox
Eric Stanton
Maher Tahhan

Instructor:
Dr. Christopher Palmstrøm
Teaching assistants:
Anthony Mcfadden and Mihir Pendharkar
Lab supervisor:
Bob Hill

“If we knew what it was we were doing, it would not be called research, would it?”
- Albert Einstein

Fabrication of NMOS Transistors
by
Group 7:
Merve Albayrak
Andreas De Groote
Gary Fox
Eric Stanton
Maher Tahhan

Abstract
Starting from a bare p-doped silicon wafers NMOS transistors were made using oxidation, phosphorous
diffusion and basic photolithographic mask and etch steps. Resistors, capacitors and diodes were made as
test structures. The measurements taken during the fabrication show accurate alignment (error of ±1µm)
and layer thicknesses, showing good understanding and skill of the cleanroom equipment. Transmission
line measurements showed that the ohmic contacts had a resistance of 8.65 Ω and a sheet resistivity of
24.42 Ω/ . The diodes did not show the typical Shockley characteristic, but were resistive. From this, it
was hypothesized the samples were doped too heavily with phosphor, causing the depletion region to be
misaligned with respect to the metal contacts. The diode capacitance did indicate a depletion region, as
the metal still overlaps depletion region. The transistors with channel lengths over 10µm showed typical
MOSFET characteristics, be it with a negative threshold voltage, but the ones of 5µm did not work. Both
these results can probably be attributed to the excess doping or trapped charges. The capacitance of the MOS
capacitors was found to be constant due because they might already have been at the verge of inversion.

ii

Contents
1 Introduction

1

2 Fabrication Procedure

2

3 Results and Discussions
3.1 TLM and Wafer Resistance . . . . . . . . . . . . .
3.2 Diodes . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 NMOS Current Voltage Characteristics . . . . . .
3.3.1 Drain Current vs. Drain to Source Voltage
3.3.2 Drain Current vs. Gate Voltage . . . . . . .
3.4 Capacitor . . . . . . . . . . . . . . . . . . . . . . .

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4 Conclusion

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Bibliography

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iii

Chapter 1

Introduction
The primary objectives of this lab are to understand, develop, and practice the techniques in order to
develop semiconductor devices and test them for their electrical characteristics. N-channel MOSFETs, pMOS capacitors, diodes, and resistors are processed on p-type silicon. This is done using photolithography
using four masks provided. SiO2 is grown using wet and dry thermal oxidation. Phosphorous is doped to
form n+ regions using a diffusion funace. Aluminum contacts are deposited using thermal vapor deposition.
To test the quality of the processing, current-voltage and capacitance-voltage relations of the diodes, MOS
capacitors, resistors, and MOSFETs are characterized. Key values are extracted from the characteristic
curves. The threshold and flatband voltages are calculated from the capacitance between the gate and source
of the MOSFETs. The threshold voltage is also extracted from the drain current curve.
Non-idealities and major issues in the devices are examined and from this the early voltage, a measure of
channel length modulation, is determined. Characteristics of devices that do not perform are examined to
assess the possible causes of failure.

1

Chapter 2

Fabrication Procedure
The entire process is illustrated in figure 2.1, as well as a schematic of the cross section of a transistor and an
indication of where measurements were taken. All steps are standard process steps in typical cleanroooms,
also described in [1], [2] and [3].
The process was started from two blank p-doped < 100 > silicon wafers with lot number 4P010-20SSP-INV.
The wafer was cleaved in four equal samples that were carried through the procedure, either as lead sample or
as actual high-end sample. The resistivity was measured to be 18.51 ± 0.68 Ω-cm, which is in the boundaries
of the predicted 10 to 30 Ω-cm indicating this is a good wafer to process on.
To prepare the wafer for the growth of the oxide mask used in the phosphorous diffusion, a piranha clean was
carried out for 10 minutes at 100 ◦ C. After this, a wet oxide was grown for 85 minutes at 1000 ◦ C between
two dry oxidations of 10 minutes at 1000 ◦ C. The oxide thickness after this step was measured to be 5379 ±
67 ˚
A using the filmetrics thin film thickness measurement tool. As it was 5000 ˚
A which was aimed for, the
oxidation time should have been shorter by 3-4 minutes. As this oxide serves as a mask and part of the field
oxide later, a thicker oxide is not going to cause any problems. [4]
The first mask to be applied was the mask for phosphorous diffusion. After a standard cleaning step a
photoresist mask was applied [1], including a descum for one minute. To etch the oxide mask, the samples
were dipped in 10:1 DI H2 O:HF for 12 minutes with agitation. The photoresist was stripped and the oxide
thickness was measured to be 5350 ˚
A using the Dektak profilometer, confirming the result found earlier.
The next step was to carry out the phosphorous diffusion, creating the source and drain regions of the
transistors, the n-side of the diodes and well of the MOS capacitor.[5] After a standard clean, the samples
were cleaned in piranha for 10 minutes at 100 ◦ C. In order to be sure no native oxide was formed between
this step and the etch of the oxide mask, a one minute buffered HF dip was done. The samples were loaded
in the diffusion furnace and were doped for 30 minutes at 950◦ C. Following this, the phosphorous glass was
etched off in 10:1 DI H2 O:HF for 6 minutes. The removal was checked visually as the water did bead on
the surface, indicating a hydrophobic surface. Using a calculated value of 1.3 µm for the junction depth, the
resistivity of a test sample was measured to be 32 ± 7 mΩ-cm, which is well below the initial value indicating
phosphor had indeed diffused into the samples.[6], [7], [8]
The anneal was done in the oxidation furnace in a sequence of dry - wet - dry oxidation of respectively 10,
40 and 10 minutes at 1000◦ C. After this, also an anneal was done in N2 for 10 minutes at 1000 ◦ C. This step
did not only drive in the dopants, but also increased the field oxide thickness and created a gate pre-oxide.
2

Chapter 2. Fabrication Procedure
1

3
Standard clean
M

Piranha clean

4

Standard clean

PR mask
Oxidation

SiO2
Si

M

2

HF etch

Standard clean
Strip
PR mask
Piranha

Photoresist

HF etch
Oxidation
Strip PR
M

3

5

Standard Clean

Standard clean
PR mask
Piranha clean
HF etch
HF etch
Strip
Phosphor diffusion

P-doped Si

PR mask

Aluminum

P-glass removal
M

Metal evaporation

Oxidation
M

Lift off

Figure 2.1: Schematic of fabrication procedure with a schematic of the transistor cross section. Also the points of
measurements are indicated.

The gate pre-preoxide was measured to be 3720 ˚
A using the Dektak profilometer. The field oxide thickness
was not measured but can be expected to be ± 6800 ˚
A, i.e. more than enough to ensure isolation between
the different devices and the gate and source or drain metals.
After the creation of doped source and drain regions and field oxide growth, the gate oxide had to be formed.
For this, a photoresist mask was applied after a standard clean and the gate pre-oxide is etched off in a dip of
3.5 minutes in buffered HF. In order to be sure that the silicon substrate is reached, steps of 30 seconds were
carried out and the depth of the etch was monitored. After the stripping of the photoresist and a piranha
clean of 7 minutes at 100 ◦ C, the gate oxide was formed in a 70 minute dry oxidation. Using the Dektak
profilometer, the gate oxide thickness was measured to be 430 ˚
A.
At this point, the different regions were defined and all that was left is ensure good contacts. After a standard
clean, a photoresist via mask was applied and the source and drain vias were etched in buffered HF for 11

Chapter 2. Fabrication Procedure

4

minutes. Again, in this were some smaller steps included to ensure good contact with the silicon. The
photoresist was stripped and new photoresist was immediately again applied for the metal lift-off mask. In
order to have enough overhang, a toluene soak of 5 minutes was performed before developing. Next, 2881
˚
A was evaporated, as measured by the crystal sensor in the evaporator. In order to protect the gate oxide, no
HF etch was performed before the metal evaporation. Therefore, to prevent a thick native oxide, the steps
between the via etch and the metal evaporation were carried out as fast as possible. The final step was to lift
off the metal. For this the samples were soaked in acetone for 15 minutes with mild agitation, followed by
five steps of 10 seconds ultrasonic agitation. As the first I-V measurements showed ohmic contacts no extra
anneal to drive in the aluminum was carried out. [9]
Figure 2.2 shows the alignment of the different masks at the outer edges of the samples. As can be seen,
both have an alignment within the margin of one micron for all masks. The fact that this is true for both
corners indicates also the tilt error is very low. To conclude this section, figure 2.3 shows a cross section of the
MOSFET gate along the width. The different structures are indicated on this figure as well. Unfortunately
the quality of the SEM is too low to inspect the cross section.

(a) Top right corner of the sample

(b) Bottom left corner of the sample

Figure 2.2: Vernier scales to measure the misalignment of the different masks

Figure 2.3: SEM image of the gate of a MOS transistor

Chapter 3

Results and Discussions
3.1

TLM and Wafer Resistance

The sheet resistance, contact resistance, and specific contact resistance of the p-type silicon substrate are
obtained with the transmission line measurement technique (TLM). Multiple resistance measurements are
taken between two metal contacts connected by a strip of silicon for multiple lengths of silicon. If this
resistance is plotted as a function of the length of silicon measured, then the slope yields the sheet resistance
and the extrapolated point at zero length of silicon yields the contact resistance, as shown in equations 3.1,
3.2 and 3.3 where W is the width of the metal contact, 100 µm, and LT is the transfer length over which
current transfers from the metal contact to the semiconductor [10].

R(L)

=

R(L = 0)

=

Rsheet

=

Rsheet
× (L + 2LT )
W
2Rcontact
Rcontact × W
LT

(3.1)
(3.2)
(3.3)

The specific contact resistance of the silicon can then be calculated from the sheet resistance and the transfer
length as shown in equation 3.4.

ρc

= Rsheet × L2T

(3.4)

Figure 3.1 plots the TLM resistances versus the length of the silicon between contacts as described by
equations 3.1, 3.3, and 3.4 for two different die locations on the wafer. The slope of this plot is proportional
to the sheet resistance. Extrapolating the linear approximation to the x-intercept yields the transfer length
and y-intercept value yields the contact resistance. These calculated values are shown in table 3.1.
Figure 3.2 shows an I-V plot of one of the 80 µm TLM contact separation points, which verifies that the
I-V curve is linear between ±50 mV and the contact is ohmic. The I-V curves for all the TLM resistance
measurements similarly showed linear plots so an annealing step was not necessary to decrease the Schottky
barrier width and promote tunneling.[11] It is possible that the deposition of aluminium by thermal evaporation actually provided some annealing since three cartridges of aluminium were used in the deposition. The
5

Chapter 3. Results and Discussions

6

Table 3.1: Calculations for the contact resistance, sheet resistance, transfer length, and specific contact resistance
at two locations on the wafer and the average value for each

Standard error
Rcontact
Rsheet
LT
ρc

Position 1
3.8 Ω
8.19 Ω
22.39 Ω/
36.57 µm
0.0300 Ωcm2

Position 2
22.0 Ω
9.11 Ω
26.44 Ω/
34.46 µm
0.0314 Ωcm2

(a) First position

Average
N/A
8.65 Ω
24.42 Ω/
35.52 µm
0.0307 Ωcm2

(b) Second position

Figure 3.1: TLM measurements with linear fit

2

Measurement
Linear fit

I (mA)

1
0
−1
−2
−0.05

0
V (V)

0.05

Figure 3.2: I-V plot of 80µm separation TLM resistor element

second and third evaporations could have heated the first layer of aluminium deposition enough to slightly
anneal the layer. Also, a higher dopant concentration could have decreased the width of the Schottky barrier
enough to allow tunneling, consequently creating a ohmic contact.
Figure 3.3 shows the resistance measured on the 80 µm TLM contact separation point for each die. The
phosphorous diffusion was not uniform, which is represented by the high standard deviation value (about 33%

Chapter 3. Results and Discussions

7

of the mean value) shown in the statistical data of the wafer resistance in table 3.2. Also, the wafer resistance
values at locations (4,1) and (4,2) are higher than the wafer resistance values at all other locations. There
is clearly a trend in the wafer resistance, as shown in figure 3.3, which corresponds to the non-uniformity in
the phosphorous diffusion.
Table 3.2: Statistical values for the resistance across the wafer

Average
Standard Deviation

Wafer Resistance Statistics
48.67 Ω
15.99 Ω

Figure 3.3: Resistance measurements across the wafer after phosphorous diffusion

3.2

Diodes

The diode fails to demonstrate proper I-V characteristics normally associated with p-n junctions. The
behavior is expected to resemble the curve of the Shockley equation 3.5. None of the diodes show this
characteristic. VD is the voltage across the diode, ID is the current through the diode, and IS is the saturation
current of the diode.
 qVD

ID = IS e kT − 1

(3.5)

Overdoping is likely to be the cause of this behavior. Extension of the n+ doping profile is estimated to
extend close to or beneath the cathode contact edge, causing a depletion region to be located too close to
the cathode contact edge. As the curve is neither symmetric around zero in figure 3.4b nor exhibits even
slight diode behavior, there must be some parasitic effects dominating and requires a more complex model
to explain this behavior. Changing the lighting conditions on the sample did not have any effect on the
characteristics.
The capacitance curves for the diode appear similar to what is expected. There is a clear depletion capacitance
at negative bias, and a diffusion capacitance at positive bias. The depletion capacitance for the 1000 µm
diodes is about 104 pF. The diffusion capacitance settles around 144 pF.

Chapter 3. Results and Discussions

8

0.01

0.1

0.005

Current (A)

Current (A)

0.05
0
−0.005

0

−0.01
−0.05
−0.015
−0.02
−20

−15

−10
−5
Voltage (V)

0

5

−0.1
−10

−5

0

5

Voltage (V)

(a) 1000 µm x w µm diodes

(b) 10580 µm x w µm diodes

Figure 3.4: I-V characteristics for diodes in the MOS structure
−10

1.6

x 10

1.5
Capacitance (F)

1.4
1.3
1.2
1.1
1
0.9
0.8
−10

−5

0
Bias voltage (V)

5

10

Figure 3.5: C-V characteristics for 1000 µm x w µm diodes in the MOS structure

As previously demonstrated [2], phosphorous diffusion is difficult to control, and is a strong candidate to the
cause of this phenomenon. It is possible that the phosphorous doped region extends from the first contact
into the depletion region of the metal-semiconductor interface of the second contact. In this case, there would
still be a depletion capacitance and the I-V curve will not be diode characteristic. This behavior is complex
and the junction should be modeled using differential discrete components in order to make a simulation that
would verify the hypothesis.

3.3

NMOS Current Voltage Characteristics

MOSFET current-voltage characteristics give critical information on the operation of the device. Ideal
N-channel MOSFETs, ignoring short channel effects, leakage, and nonuniformity effects, obey specific relationships for linear and saturation regimes. VT is the threshold voltage, VG is the gate bias, VDS is the drain
to source voltage, and ID is the drain current. When VG < VT , the device is in cutoff and allows no current
to pass through the drain. When VG > VT and VG − VT > VDS , the device is in the linear regime and follows
figure 3.6. However if VG > VT and VG − VT < VDS , the device is in saturation and ideally does not depend

Chapter 3. Results and Discussions

9

on VDS as seen in figure 3.7 for the current in saturation.

ID

=

ID

=



1 2
W
(VG − VT )VDS − VDS
µn Cox
L
2
1
W
µn Cox (VG − VT )2
2
L

(3.6)
(3.7)

In the above equations, µn is the electron mobility in the semiconductor, Cox is the gate oxide capacitance,
W is the width of the channel, and L is the length of the channel.

3.3.1

Drain Current vs. Drain to Source Voltage

Sweeping the voltage across the drain and source and varying gate voltages show the linear and saturation
behavior of the MOSFETs. As figure 3.6 shows, with increased gate voltage, the saturation current increases.
There is still some resistance during saturation which gives a slope in the current. The curves show a clear
linear region at low voltages. In reverse drain bias, the device is still in the linear regime with the source and
drain reversing functions and the gate at a constant voltage above the source, which now acts as the drain.

Figure 3.6: VDS sweep at VG from -2 V to 5 V in 1 V steps

To characterize the slope in the drain current during saturation, a value called the Early voltage is used.
This is the x-intercept of the line through the saturation current with respect to drain voltage. In the case
of the 100x10 µm transistor, the Early voltage (VA ) is about -30 V. For all of the transistors, VA varies from
-30 V to -53 V. It appears that the Early voltage is dependant on the gate length and not the width. This
is reasonable as the Early voltage is an effect of channel length modulation. The effective channel length
decreases as VDS increases since the inverted channel depth increases, decreasing the channel resistance.
Table 3.3 shows the gate voltages measured for the transistor sizes.
Note however that the lowest gate voltage is -2 V. The device is able to turn on when the gate voltage is 0 V.
This indicates that either there is a large leakage current or that this is a depletion mode device. To confirm
this, the threshold voltage needs to be calculated.

Chapter 3. Results and Discussions

10

Table 3.3: VA measured for each transistor size

Gate Length
10 µm
15 µm
20 µm

3.3.2

100 µm
-30 V
-40 V
-49 V

Gate Width
200 µm 400 µm
-30 V
-30 V
-40 V
-46 V
-51 V
-53 V

Drain Current vs. Gate Voltage

The turn-on characteristics can be seen by sweeping the gate voltage at a low drain to source voltage. This
attempts to keep the transistor in the linear region with VG larger than VDS for most of the curve. The
curve, as seen in figure 3.7, gives very little current until VG reaches a certain voltage and begins to increase.
This voltage is the threshold voltage (VT ). To determine the threshold voltage, the transconductance gm ,
or partial derivative of ID w.r.t. VG is plotted as in 3.8 and the maximum is found to get the inflection
point, where the curve is most linear, and this is extrapolated back to find the threshold. For the 100x10 µm
transistor, VT = −1.3V . As mentioned before, the sweep of VDS showed either a negative threshold or large
leakage. This confirms the negative threshold of the device. The thresholds of the other devices are found in
table 3.4.

Figure 3.7: Current for VG sweep at VD = .1V

Figure 3.8: Transconductance for VG sweep at
VD = .1V

Table 3.4: VT measured for each transistor size

Gate Length
10 µm
15 µm
20 µm

100 µm
-1.30 V
-1.34 V
-1.40 V

Gate Width
200 µm 400 µm
-1.25 V -1.17 V
-1.23 V -1.12 V
-1.20 V -1.15 V

The negative threshold can be attributed to several possible factors. The phosphorous n-type doping may
have diffused much further than intended causing the channel to be lightly n-doped without a gate bias.

Chapter 3. Results and Discussions

11

Another possibility is that there are trapped charges at the oxide-channel interface. These occur when
the interface is not smooth, quantizing the states which the electrons, or majority carriers, can occupy in
the channel. The electrons become trapped in wells at the interface if they cannot receive enough energy
to escape. When the transistor is turned on again, the carriers are already present without inverting the
channel.
There appears to be a trend between gate width and threshold voltage, independent of the gate length. The
threshold voltage decreases as the gate width increases for each gate length. Although this trend is evident,
the threshold voltage may not be dependent on the gate length since other factors, such as phosphorous
diffusion non-uniformity, may instead create this trend.
The Id versus VG plot of the 5 µm gate transistors showed little dependence of the drain current to the gate
voltage. Although the current showed a slight slope over the gate voltage sweep, the current was nearly
constant and therefore was not characteristic of an NMOS transistor. Consequently, the Early and threshold
voltages were not calculated for the 5 µm gate transistors.

3.4

Capacitor

135

800

130

790
Capacitance (pF)

Capacitance (pF)

The results for C-V measurement to determine the flat-band voltage are shown in figure 3.9 for both 100 µm
x 100 µm and 1000 µm x 1000 µm capacitors.

125
120
115
110
−5

780
770
760

0
Bias voltage (V)

(a) 100 µm x 100 µm MOS capacitance

5

750
−5

0
Bias voltage (V)

5

(b) 1000 µm x 1000 µm MOS capacitance

Figure 3.9: C-V characteristics of the MOS capacitances

This figures don’t allow one to make conclusions about flat-band voltage because C-V characteristics curve
for a MOS structure should include inversion, depletion and accumulation regions. It is known that total
capacitance of the MOS structure consists of oxide layer capacitance (Cox ) and depletion layer capacitance
(CD ). Yet, when examining the C-V curve, one realizes that there is no depletion layer. The reason could
be something providing negative charge which reduces the depletion capacitance’s effect. It may instead be
that in thermal equilibrium the capacitor is on the verge of inversion, or at the threshold voltage, i.e. the
fermi level and the intrinsic level at the edge of the depletion region are very close to each other. This would
cause the depletion regime to occur at a very narrow range of biases. If this is too narrow, the effects of the
depletion capacitance may not be seen.

Chapter 3. Results and Discussions

12

The curves for gate to source capacitance (CGS ) for the 200 µm x 20 µm MOSFET are in 3.10. The values
extracted from the all gate to source capacitance curves for differently sized MOSFETs are found in 3.5. When
the negative voltage is applied to the gate, majority carriers (holes) accumulate on the Si-SiO2 surface, so
this region is called as accumulation region. In this region, CD is negligible so gate to source capacitance is
equal to Cox and the obtained values for Cox are shown in 3.5.

Capacitance (pF)

119

118.5

118

117.5

117
−10

−5

0
Bias voltage (V)

5

10

Figure 3.10: C-V characteristics for 200 µm x 20 µm CGS in the MOS structure

Table 3.5: Key values from CV curves

Transistor size
(WxL)
100x05 µm
100x10 µm
100x15 µm
100x20 µm
200x05 µm
200x10 µm
200x15 µm
200x20 µm
400x05 µm
400x10 µm
400x15 µm
400x20 µm

Cox
80.4 pF
114.8 pF
109.1 pF
98.2 pF
117.1 pF
118.2 pF
118.7 pF
118.8 pF
118.9 pF
120.2 pF
121.9 pF
124.4 pF

capacitance in depletion
77.5 pF
114.3 pF
108.4 pF
93.3 pF
116.8 pF
117.5 pF
117.4 pF
117.0 pF
118.5 pF
118.9 pF
119.5 pF
120.7 pF

VF B
-0.8 V
-0.4 V
-0.4 V
-0.4 V
4.4 V
0V
0.4 V
-1.2 V
5.2 V
0.4 V
0V
0.4 V

When the applied voltage increases, the majority carriers are repelled from the SiO2 surface. Acceptor ions
remain as fixed charges, forming the depletion region. In this regime, gate to source capacitance is affected
by both Cox and CD . As the channel enters the depletion regime, the depletion width increases and CD
decreases making the total capacitance during depletion smaller.
When the flatband voltages were extracted, some unreasonable values are found, in particular, positive
flatband voltages. The reason for this could be excess amount of diffusion or charge traps. Note that the
effect was clear for all transistors, but rather small.

Chapter 4

Conclusion
In this lab project MOSFETs, capacitors and resistors were fabricated and tested. The fabrication was done
using standard fabrication techniques, such as photolithography, phosphorous diffusion, and oxidation.
Basic tests during the fabrication verified that previous processing steps were successful before continuing to
the next process. The mask mis-alignment was measured on the vernier scales to be no greater than 1 µm
in either the vertical or horizontal direction after each lithography step. Oxide thickness was measured after
each growth and the gate oxide was measured to be 430 ˚
A.
TLM measurements showed ohmic contacts were achieved without extra annealing, probably because of
crossheating of the different aluminium sources. The contact resistance was measured to be 8.65 Ω, the sheet
resistance 24.42 Ω/ .
The diodes did not show the typical Shockley relation between current and voltage. This could be attributed
to an excess amount of phosphor atoms moving the depletion region outside of the relevant region. The
capacitance of the diode did show the effect of a changing depletion region width with varying applied
voltage. The combination of these measurements indicates a more complex interplay between the contact
metal and the depletion region.
Typical MOSFET characteristics were obtained from the transistors, be it with a negative threshold. The
origin of this negative threshold lies in trapped charges or excess doping below the gate. There was also a
trend observed of the threshold voltage dependence on the gate width, which does not correspond to basic
theory. Reasons for this are still unclear. The MOSFETs with the shortest lengths did not work. Because of
previous measurements, the most probable malefactor would be an excess doping, connecting the source and
drain.
The capacitance of the MOS capacitors was measured to be nearly constant as a function of the applied
bias voltage. Also this is probably due to the excess doping profile, ensuring the device is on the verge of
collapsing even in so-called depletion regime, meaning that the effect of the changing depletion region is very
small. The capacitance of the transistor did exhibit the typical interplay of accumulation-depletion-inversion
regions. Still, also here the effect is small and some strange values for the flatband voltage were found.
Clearly, it can be concluded that there is an excess amount of phosphorus diffusion. When the diode IV characteristics, MOS capacitor C-V characteristics, negative threshold voltage of MOS transistors and
nonfunctioning small devices with 5 µm size are all considered, it is understood that these all resulted from
13

Chapter 4. Conclusion

14

excess amount of phosphor diffusion. This problem can only be solved by shortening the diffusion time, but
even then this will stay a factor of high uncertainty because of the thermal budget of the steps after the
doping.
Techniques were learned in measurement, theory, and production. In addition, skills for future fabrication
using teaching clean room equipment and relevant device design approaches were effectively cultivated. Although working devices were fabricated, the process was hard to control, especially the phosphorous diffusion.
During the testing, the problems were identified and can be tackled in next process runs.

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