Intel Yan Borodovsky SPIE 2006 .pdf
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Marching to the Beat of
Moore’s Law
Yan Borodovsky
Portland Technology Development
Intel Corporation
Hillsboro, Oregon, USA
SPIE Microlithography 2006, San Jose, Ca USA
1
“ The Definition of “Moore’s Law” has
come to refer to almost anything related
to the semiconductor industry that when
plotted on semi-log paper approximates a
straight line”
Gordon Moore
Plenary Talk
February 19, 1995
E-Beam, X-Ray, EUV and I-beam
Lithography for Manufacturing V
Santa Clara, Ca USA
SPIE Microlithography 2006, San Jose, Ca USA
2
Moore’s 1965 insight:
“ I wanted to get across the idea that integrated
circuits were a way to make electronics cheap.
You could see the technology was going to let
you make more complex things and the costs
were going to go down.
That was really the message I wanted to get
across.”
Gordon Moore
San Jose Mercury News
April 2, 2005
SPIE Microlithography 2006, San Jose, Ca USA
3
Exponential Complexity Growth
Intel Microprocessors Complexity 1971 -2006
N
Intel®ItaniumTM2 (90nm)
Transistors Count
Intel®Itanium®2
Intel®Itanium®2
Intel®Pentium®
Intel486TM
Intel386TM
Intel®PreslerTM
Intel®
CoreTMDuo
Intel®Pentium®4
Intel®Pentium®II
109
108
107
Intel®Pentium®III
106
286
105
8086
4004
104
8080
8008
1970
1975
103
1980
1985
1990
1995
2000
2005
SPIE Microlithography 2006, San Jose, Ca USA
2010
2015
4
Exponential Complexity Growth
Intel Microprocessors Complexity 1971 -2006
N
Intel®ItaniumTM2 (90nm)
Transistors Count
Intel®Itanium®2
Intel®Itanium®2
Intel®Pentium®
Intel486TM
Intel386TM
Intel®PreslerTM
108
Intel®
CoreTMDuo
Intel®Pentium®4
Intel®Pentium®II
109
107
Intel®Pentium®III
106
286
N=30*2^((Y-1960)/2)
8086
4004
8080
N Doubles every 2 years
8008
1970
105
1975
1980
1985
1990
1995
2000
2005
SPIE Microlithography 2006, San Jose, Ca USA
2010
104
103
2015
5
Exponential Cost Reduction
Cost per Transistor
SPIE Microlithography 2006, San Jose, Ca USA
6
Exponential Cost Reduction
Cost per Transistor
$/N=$30*2^-((Y-1960)/1.55)
SPIE Microlithography 2006, San Jose, Ca USA
7
Exponential Cost Reduction
Cost per Transistor
$/N halves every 19.6 month)
SPIE Microlithography 2006, San Jose, Ca USA
8
Exponential Cost Reduction
Value to End User
With permission from
IC Knowledge LLC
SPIE Microlithography 2006, San Jose, Ca USA
9
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