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COMPUTER ORGANIZATION

10CS46

parallel adder an nth stage adder can not complete the addition process before all its
previous stages have completed the addition even with input bits ready. This is because,
the carry bit from previous stage has to be made available for addition of the present
stage.

In practice, a number of design techniques have been used to implement highspeed adders. In order to reduce this delay in adders, an augmented logic gate network
structure may be used. One such method is to use circuit designs for fast propagation of
carry signals (carry prediction).
Carry-Look ahead Addition:

As it is clear from the previous discussion that a parallel adder is considerably
slow & a fast adder circuit must speed up the generation of the carry signals, it is
necessary to make the carry input to each stage readily available along with the input bits.
This can be achieved either by propagating the previous carry or by generating a carry
depending on the input bits & previous carry. The logic expressions for si (sum) and c i+1
(carry-out) of stage ith are

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