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1 |CAO - I n s t r u c t i o n s

The memory consists of many millions of storage cells, each of which can store a bit of information
having the value 0 or 1. Because a single bit represents a very small amount of information, bits are
seldom handled individually. The usual approach is to deal with them in groups of fixed size. For this
purpose, the memory is organized so that a group of n bits can be stored or retrieved in a single, basic
operation. Each group of n bits is referred to as a word of information, and n is called the word
length. The memory of a computer can be schematically represented as a collection of words, as
shown in Figure.
Modern computers have word lengths that typically range from 16 to 64 bits. If the word length of a
computer is 32 bits, a single word can store a 32-bit signed number or four ASCII-encoded characters,
each occupying 8 bits.
A unit of 8 bits is called a byte.
Accessing the memory to store or retrieve a
single item of information, either a word or a
byte, requires distinct names or addresses for
each location. It is customary to use numbers
from 0 to 2k− 1, for some suitable value of k, as
the addresses of successive locations in the
memory. Thus, the memory can have up to 2k
addressable locations. The 2k addresses
constitute the address space of the computer.
For example, a 24-bit address generates an
address space of 224 (16,777,216) locations.

First word
Second word
ith word
Last word

This number is usually written as 16M (16 mega),
where 1M is the number 220 (1,048,576).
A 32-bit address creates an address space of 232
or 4G (4 giga) locations, where 1G is 230 . Other
notational conventions that are commonly used
are K (kilo) for the number 210 (1,024), and T
(tera) for the number 240

S0903 | KITS – WGL 2012


2 | CAO - I n s t r u c t i o n s

A byte is always 8 bits, but the word length typically ranges from 16 to 64 bits. It is impractical to
assign distinct addresses to individual bit locations in the memory. The most practical assignment is
to have successive addresses refer to successive byte locations in the memory. This is the
assignment used in most modern computers. The term byte-addressable memory is used for this
assignment. Byte locations have addresses 0, 1, 2,.... Thus, if the word length of the machine is 32
bits, successive words are located at addresses 0, 4, 8,..., with each word consisting of four bytes.
There are two ways that byte addresses can be assigned across words, as shown in Figure.
The name big-endian is used when lower byte addresses are used for the more significant bytes
(the leftmost bytes) of the word.
The name little-endian is used for the opposite ordering, where the lower byte addresses are used
for the less significant bytes (the rightmost bytes) of the word.
The words “more significant” and “less significant” are used in relation to the weights (powers of 2)
assigned to bits when the word represents a number.
Both little-endian and big-endian assignments are used in commercial machines. In both cases, byte
addresses 0, 4, 8,..., are taken as the addresses of successive words in the memory of a computer
with a 32-bit word length. These are the addresses used when accessing the memory to store or
retrieve a word.




Byte address






(a) Big endian assignment



Byte address




(b) Little endian assignment

In addition to specifying the address ordering of bytes within a word, it is also necessary to specify
the labeling of bits within a byte or a word. The most common convention, and the one we will use
in this book, is shown in Figure below. It is the most natural ordering for the encoding of numerical
data. The same ordering is also used for labeling bits within a byte, that is, b7, b6,..., b0, from left to
b31 b30

. . . . .

Sign bit: b31 = 0 for positive numbers
b31 = 1 for negative numbers
(a) A signed integer
S0903 |CSE KITS – WGL 2012

b1 b0

3 | CAO - I n s t r u c t i o n s


ASCII character



ASCII character

ASCII character


ACSII character

(b) Four characters

Examples of encoded information in a 32-bit word.

Storing Words in Memory
We've defined a word to mean 32 bits. This is the same as 4 bytes. Integers, single-precision
floating point numbers, and MIPS instructions are all 32 bits long. How can we store these values
into memory? After all, each memory address can store a single byte, not 4 bytes.
The answer is simple. We split the 32 bit quantity into 4 bytes. For example, suppose we have a 32
bit quantity, written as 90AB12CD16, which is hexadecimal. Since each hex digit is 4 bits, we need 8
hex digits to represent the 32 bit value.
So, the 4 bytes are: 90, AB, 12, CD where each byte requires 2 hex digits. This hexadecimal is stored
in memory using Big endian and little endian assignments of 8-bit format with the starting address
1000 are given below


Word Alignment
In the case of a 32-bit word length, natural word boundaries occur at addresses 0, 4, 8,..., We say
that the word locations have aligned addresses if they begin at a byte address that is a multiple of
the number of bytes in a word. For practical reasons associated with manipulating binary-coded
addresses, the number of bytes in a word is a power of 2. Hence, if the word length is 16 (2 bytes),
aligned words begin at byte addresses 0, 2, 4,..., and for a word length of 64 (23 bytes), aligned
words begin at byte addresses 0, 8, 16,.... There is no fundamental reason why words cannot begin
at an arbitrary byte address. In that case, words are said to have unaligned addresses. But, the most
common case is to use aligned addresses, which makes accessing of memory operands more
Accessing Numbers and Characters
A number usually occupies one word, and can be accessed in the memory by specifying its word
address. Similarly, individual characters can be accessed by their byte address. For programming
convenience it is useful to have different ways of specifying addresses in program instructions.

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4 | CAO - I n s t r u c t i o n s

In many applications it is necessary to handle character strings of variable length. The beginning of
the string is indicated by giving the address of the byte containing its first character. Successive byte
locations contain successive characters of the string. There are two ways to indicate the length of
the string. A special control character with the meaning “end of string” can be used as the last
character in the string, or a separate memory word location or processor register can contain a
number indicating the length of the string in bytes.

The different ways in which the location of an operand is specified in the instruction are
referred to as “addressing modes”. Different opcodes will use different addressing modes.
MODE FIELD: One or more bits in the instruction format can be used as a mode field. The value of
the mod field determines which addressing mode is to be used.
EFFECTIVE ADDRESS: In a system without virtual memory, the effective address (EA) will be either a
main memory or a register. In a virtual memory system, the effective address is a virtual address or
a register.
Computers use addressing mode techniques for the purpose of accommodating one or both
of the following reasons:
1. To give the programming versatility to the user by providing such facilities as pointers to
memory, counters for loop control, indexing of data and program relocation.
2. To reduce the number of bits in the addressing field of the instruction

The simplest form of addressing is immediate addressing, in which the operand value is present in
the instruction.
Operand = A


This mode can be used to define and use constants or set initial values of variables. Typically the
numbers will be stored in two’s complement form. The left most bit of the operand field is a sign
The advantage of the immediate addressing mode is that no memory reference other than the
instruction fetch is required to obtain the operand, thus saving the memory or cache cycle in the
instruction cycle. The disadvantages is that the size of the number is restricted to the size of the
address field, which, in most instruction sets, is small compared with the word length.


Move 200,R0

S0903 |CSE KITS – WGL 2012

places the value 200 in register R0

5 | CAO - I n s t r u c t i o n s

A very simple form of addressing is the direct addressing, in which the address field contains the
effective address of the operand.
EA = A


The technique was common in earlier generations o f the computers but is not common on
contemporary architectures. It requires only one memory reference and no special calculation. The
obvious limitation is that it provides only a limited address space, this is because the length of the
address field is less than the word length.

Move LOC, R2

In this technique the address field refers to the address of a word in the memory, which in turn
contains a full-length address of the operand. This is known as indirect addressing.
EA = (A)

the parenthesis indicates “contents of”


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6 | CAO - I n s t r u c t i o n s

The obvious advantage of this approach is that for a word length of N, an address space of 2 N is
now available. The disadvantage is that instruction execution requires two memory references to
fetch the operand: one to get its address and a second to get its value.
Although the number of words that can be addressed is now equal to 2N, the number of different
effective addresses that may be referenced to any time is limited to 2 K, where K is the length of the
address field.

Add (A),R0

Register addressing is similar to direct addressing. The only difference is that address field refers to
a register rather than a main memory address.
EA = R
To clarify, if the contents of a register address field in an instruction is 5, then register R5 is the
intended address, and the operand value is contained in R5. Typically an address field that
references registers will have from 3 to 5 bits, so that a total of from 8 to 32 general-purpse
registers can be referenced.


The advantages of registering addressing are that (1) only a small address field is needed in the
instruction. (2) No time consuming memory references are required.
The disadvantage of register addressing is that the address space is very limited.
If register addressing is heavily used in an instruction set, this implies that the processor registers
will be heavily used. Because of the severely limited number of registers, their use in this fashion
makes sense only if they are employed efficiently. If every operand is brought into a register from
main memory, operated at once, and then returned to main memory, then a wasteful immediate
step has been added. If instead, the operand in a register remains in use for multiple operations,
then a real saving is achieved.

Add R1,R2

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7 | CAO - I n s t r u c t i o n s

Just as register addressing is analogous to direct addressing, register indirect addressing is
analogous to indirect addressing. In both cases, the only difference is whether the address field
refers to a memory location or a register. Thus for register indirect address,
EA = (R)

The advantages and limitations of register indirect addressing are basically same as for indirect
addressing. In both the cases, the address space limitation (limited range of addresses) of the
address field is overcome by having that field refer to a word length location containing an address.
In addition, register indirect addressing uses one less memory reference than indirect addressing.

Add (R1),R0

A very powerful mode of addressing combines the capabilities of direct addressing and register
indirect addressing. It is known by a variety of names depending on the context of its use, but the
basic mechanism is the same. We will refer to this as displacement addressing:
EA = A + (R)
Displacement addressing requires that the instruction have two address fields, at least one of which
is explicit. The value contained in one address field (value = A) is used directly. The other address
field, or an implicit reference based on opcode, refers to a register whose contents are added to A
to produce the effective address.
Three of the most common uses of displacement addressing are:
Relative addressing.
Base – register addressing.
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8 | CAO - I n s t r u c t i o n s



For relative addressing, also called as PC-relative addressing, the implicitly referenced register is
the program counter (PC). That is, the next instruction address is added to the address field to
produce the effective address.
Typically the address field is treated as a two’s complement number for this operation. This
effective address is a displacement relative to the address of the instruction.
Relative addressing exploits the concept of locality. If most memory references are relatively near
to the instruction being executed, then the use of relative addressing saves address bits in the
For base register addressing, the interpretation is the following: the referenced register contains a
memory address, and the address field contains a memory address, and the address field contains a
displacement (usually an unsigned integer representation) from that address. The register
reference may be explicit or implicit.
Base register addressing also exploits the locality of memory references. It is a convenient means of
implementing segmentation. In some implementations, a single segment base register is employed
and is used implicitly. In others, the programmer may choose a register to hold the base address of
segment and the instruction must reference it explicitly. In this latter case if the length of the
address field is K and the number of possible registers is N, then one instruction can reference any
one of N areas of 2K words.
For indexing the interpretation is typically the following: The address field references a main
memory address, and the referenced register contains a positive displacement from that address.
Note that this usage is just opposite of interpretation of base-register addressing. The address field
is considered to be memory address in indexing, it generally contains more bits than an address
field in a comparable base-register instruction.
An important use of indexing is to provide an efficient mechanism for performing iterative
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9 | CAO - I n s t r u c t i o n s

The effective address of the operand is the contents of a register specified in the instruction. After
accessing the operand, the contents of this register are automatically incremented to point to the
next item in a list.
We denote autoincrement mode by putting the specified register in parenthesis, to show that the
contents of the register are used as the effective address, followed by a plus sign to indicate that
these contents are to be incremented after the operand is accessed.
Autoincrement mode is written as (Ri)+
The increment is 1 for byte-sized operands, 2 for 16-bit operands, and 4 for 32-bit operands.
The contents of a register specified in the instruction are first automatically decremented and are
then used as effective address of the operand.
We denote autodecrement mode by putting the specified register in parenthesis, preceded by a
minus sign to indicate that the contents of the register are to be decremented before being used as
the effective address.
Autoincrement mode is written as -(Ri)

A general instruction of this type has the format

Source1, Source2, Destination.

Using three address instruction, the operation C = [A] + [B] can be performed by executing the
sequence of instructions
Add A,B,C
Operands A and B are called Source operands, C is called the destination operands, and add is the
operation to be performed on the operands.
If k bits are needed to specify the memory address of each operand, the encoded form of the above
instruction must contain 3k bits for addressing purposes in addition to the bits needed to denote
the Add operation.
For a modern processor with a 32-bit address space, a 3-address instruction is too large to fit in one
word for a reasonable word length.

S0903 |CSE KITS – WGL 2012

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