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Partially Resident Textures on Next Generation GPUs.v04 .pdf


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PARTIALLY RESIDENT TEXTURES
ON NEXT-GENERATION GPUS
Bill Bilodeau, Graham Sellers, Karl Hillesland - AMD

AGENDA FOR TODAY’S TALK

Part 1 – Introduction to HD7970 and Partially Resident Textures, Bill Bilodeau
Part 2 – Implementation in OpenGL, Graham Sellers
Part 3 – Ptex, an example PRT application, Karl Hillesland

2 | Partially Resident Textures on Next-Generation AMD GPUs | March 8, 2012

PART 1
INTRODUCTION TO THE RADEON
HD7970 AND PARTIALLY RESIDENT
TEXTURES

3 | Partially Resident Textures on Next-Generation AMD GPUs | March 8, 2012

WHAT ARE PARTIALLY RESIDENT TEXTURES?
 Partially Resident Textures (PRTs) are textures that have only portions of the texture stored in GPU video
memory
 Best known example of virtual texturing (software implementation) is John Carmack’s “MegaTextures”

Image from id Software’s Rage

4 | Partially Resident Textures on Next-Generation AMD GPUs | March 8, 2012

RADEON HD7970 OVERVIEW

World’s first GPU to have dedicated hardware for Partially Resident Textures
Completely new Shader architecture
Improved cache and memory bandwidth
World’s first Direct3D® 11.1 GPU

5 | Partially Resident Textures on Next-Generation AMD GPUs | March 8, 2012

PREVIOUS SHADER ARCHITECTURE

Previous AMD GPUs used VLIW (Very Long Instruction Word) architecture
– Combines instructions into a 4-wide VLIW that gets executed on a SIMD
Shader Instructions

VLIW Instruction
X

a
b
c
d

=
=
=
=

b
c
a
d
b
e
c

+
+
+
+

c;
d;
c;
e;
a;
f;
d;

6 | Partially Resident Textures on Next-Generation AMD GPUs | March 8, 2012

Y

Z

W

b
a + c
c
a idle
d
c + d

d + e
idle

e + f
idle

Thread 0

a
b
c + c
a idle
d
c + d

d + e
idle

e + f
idle

Thread 1

b
a + c
c
a idle
d
c + d

d + e
idle

e + f
idle

Thread 2

b
a + c
c
a idle
d
c + d

d + e
idle

e + f
idle

Thread 63

NEW SHADER ARCHITECTURE

64-wide SIMD architecture without VLIW instructions
– No need to combine instructions, since multiple threads can run in parallel
Shader Instructions
a
b
c
d

=
=
=
=

b
a
b
c

+
+
+
+

c;
c;
a;
d;

ALUs

S0
b
a + c
c
a
d

S1

S2

b
a + c
c
a
d

b + d
a
c
c
a

....

No idle ALUs!

7 | Partially Resident Textures on Next-Generation AMD GPUs | March 8, 2012

S63
c + c
b
a
d

COMPUTE UNITS ARE THE NEW BASIC BUILDING BLOCK FOR SHADERS

Each Compute unit consists of 4 SIMDs and one Scalar unit
Higher execution efficiency
Simplified logic design
Simplified assembly language
HD7970 has 32 Compute Units
– 4 SIMDs per CU

Compute Unit
SQ
Instruction
SIMD0 SIMD1
Buffers/Arbiters
Scalar ALU

LDS
32 banks of
512x32
(total – 64kb)

8 | Partially Resident Textures on Next-Generation AMD GPUs | March 8, 2012

Texture Unit
(Data Section)
SIMD2 SIMD3
Texture Unit
(Addr Section)

16kb
R/W
L1

ADDITIONAL FEATURES OF THE HD7970

Improved Tessellation Performance
Improved Geometry Shader Performance
Fast depth accept for fully visible triangles, depth bounds testing support
384 bit memory bus
DX11.1
And of course, Partially Resident Texture support!

9 | Partially Resident Textures on Next-Generation AMD GPUs | March 8, 2012


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