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UM10139
Volume 1: LPC214x User Manual
Rev. 01 — 15 August 2005

User manual

Document information
Info
Keywords

Content
LPC2141, LPC2142, LPC2144, LPC2146, LPC2148, LPC2000, LPC214x,
ARM, ARM7, embedded, 32-bit, microcontroller, USB 2.0, USB device

Abstract

An initial LPC214x User Manual revision

UM10139

Philips Semiconductors
Volume 1

LPC2141/2/4/6/8 UM

Revision history
Rev

Date

Description

01

20050815

Initial version

Contact information
For additional information, please visit: http://www.semiconductors.philips.com
For sales office addresses, please send an email to: sales.addresses@www.semiconductors.philips.com
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.

User manual

Rev. 01 — 15 August 2005

2

UM10139
Chapter 1: General information
Rev. 01 — 15 August 2005 User manual

1.1 Introduction
The LPC2141/2/4/6/8 microcontrollers are based on a 32/16 bit ARM7TDMI-S CPU with
real-time emulation and embedded trace support, that combines the microcontroller
with embedded high speed flash memory ranging from 32 kB to 512 kB. A 128-bit wide
memory interface and a unique accelerator architecture enable 32-bit code execution at
the maximum clock rate. For critical code size applications, the alternative 16-bit Thumb
mode reduces code by more than 30 % with minimal performance penalty.
Due to their tiny size and low power consumption, LPC2141/2/4/6/8 are ideal for
applications where miniaturization is a key requirement, such as access control and
point-of-sale. A blend of serial communications interfaces ranging from a USB 2.0 Full
2
Speed device, multiple UARTS, SPI, SSP to I Cs and on-chip SRAM of 8 kB up to 40
kB, make these devices very well suited for communication gateways and protocol
converters, soft modems, voice recognition and low end imaging, providing both large
buffer size and high processing power. Various 32-bit timers, single or dual 10-bit
ADC(s), 10-bit DAC, PWM channels and 45 fast GPIO lines with up to nine edge or level
sensitive external interrupt pins make these microcontrollers particularly suitable for
industrial control and medical systems.

1.2 Features
• 16/32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 package.
• 8 to 40 kB of on-chip static RAM and 32 to 512 kB of on-chip flash program
memory. 128 bit wide interface/accelerator enables high speed 60 MHz operation.

• In-System/In-Application Programming (ISP/IAP) via on-chip boot-loader software. Single
flash sector or full chip erase in 400 ms and programming of 256 bytes in 1 ms.

• EmbeddedICE RT and Embedded Trace interfaces offer real-time debugging with
the on-chip RealMonitor software and high speed tracing of instruction execution.

• USB 2.0 Full Speed compliant Device Controller with 2 kB of endpoint RAM.
In addition, the LPC2146/8 provide 8 kB of on-chip RAM accessible to USB by DMA.

• One or two (LPC2141/2 vs. LPC2144/6/8) 10-bit A/D converters provide a total of
6/14 analog inputs, with conversion times as low as 2.44 µs per channel.

• Single 10-bit D/A converter provides variable analog output.
• Two 32-bit timers/external event counters (with four capture and four
compare channels each), PWM unit (six outputs) and watchdog.

• Low power real-time clock with independent power and dedicated 32 kHz clock input.
2

• Multiple serial interfaces including two UARTs (16C550), two Fast I C-bus
(400 kbit/s), SPI and SSP with buffering and variable data length capabilities.

• Vectored interrupt controller with configurable priorities and vector addresses.
• Up to 45 of 5 V tolerant fast general purpose I/O pins in a tiny LQFP64 package.
• Up to nine edge or level sensitive external interrupt pins available.
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.

User manual

Rev. 01 — 15 August 2005

3

UM10139

Philips Semiconductors
Volume 1

Chapter 1: Introductory information

• 60 MHz maximum CPU clock available from programmable on-chip PLL with
settling time of 100 µs.

• On-chip integrated oscillator operates with an external crystal in range from 1 MHz
to 30 MHz and with an external oscillator up to 50 MHz.

• Power saving modes include Idle and Power-down.
• Individual enable/disable of peripheral functions as well as peripheral clock scaling
for additional power optimization.

• Processor wake-up from Power-down mode via external interrupt, USB, BrownOut Detect (BOD) or Real-Time Clock (RTC).

• Single power supply chip with Power-On Reset (POR) and BOD circuits:
– CPU operating voltage range of 3.0 V to 3.6 V (3.3 V ± 10 %) with 5 V tolerant I/O
pads.

1.3 Applications








Industrial control
Medical systems
Access control
Point-of-sale
Communication gateway
Embedded soft modem
General purpose applications

1.4 Device information
Table 1:

LPC2141/2/4/6/8 device information

Device

Number
of pins

On-chip
SRAM

Endpoint
USB RAM

On-chip
FLASH
32 kB

Number of
10-bit ADC
channels
6

Number of Note
10-bit DAC
channels
-

LPC2141

64

8 kB

2 kB

LPC2142

64

16 kB

2 kB

64 kB

6

1

-

LPC2144

64

16 kB

2 kB

128 kB

14

1

UART1 with full modem
interface

LPC2146

64

32 kB + 8 kB [1]

2 kB

256 kB

14

1

UART1 with full modem
interface

LPC2148

64

32 kB + 8 kB [1]

2 kB

512 kB

14

1

UART1 with full modem
interface

[1]

While the USB DMA is the primary user of the additional 8 kB RAM, this RAM is also accessible at any
time by the CPU as a general purpose RAM for data and code storage.

1.5 Architectural overview
The LPC2141/2/4/6/8 consists of an ARM7TDMI-S CPU with emulation support, the
ARM7 Local Bus for interface to on-chip memory controllers, the AMBA Advanced Highperformance Bus (AHB) for interface to the interrupt controller, and the VLSI
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.

User manual

Rev. 01 — 15 August 2005

4

UM10139

Philips Semiconductors
Volume 1

Chapter 1: Introductory information

Peripheral Bus (VPB, a compatible superset of ARM’s AMBA Advanced Peripheral
Bus) for connection to on-chip peripheral functions. The LPC2141/24/6/8 configures
the ARM7TDMI-S processor in little-endian byte order.
AHB peripherals are allocated a 2 megabyte range of addresses at the very top of the
4 gigabyte ARM memory space. Each AHB peripheral is allocated a 16 kB address
space within the AHB address space. LPC2141/2/4/6/8 peripheral functions (other than
the interrupt controller) are connected to the VPB bus. The AHB to VPB bridge
interfaces the VPB bus to the AHB bus. VPB peripherals are also allocated a 2
megabyte range of addresses, beginning at the 3.5 gigabyte address point. Each VPB
peripheral is allocated a 16 kB address space within the VPB address space.
The connection of on-chip peripherals to device pins is controlled by a Pin Connect Block
(see chapter "Pin Connect Block" on page 75). This must be configured by software to fit
specific application requirements for the use of peripheral functions and pins.

1.6 ARM7TDMI-S processor
The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high
performance and very low power consumption. The ARM architecture is based on
Reduced Instruction Set Computer (RISC) principles, and the instruction set and related
decode mechanism are much simpler than those of microprogrammed Complex
Instruction Set Computers. This simplicity results in a high instruction throughput and
impressive real-time interrupt response from a small and cost-effective processor core.
Pipeline techniques are employed so that all parts of the processing and memory
systems can operate continuously. Typically, while one instruction is being executed, its
successor is being decoded, and a third instruction is being fetched from memory.
The ARM7TDMI-S processor also employs a unique architectural strategy known
as THUMB, which makes it ideally suited to high-volume applications with memory
restrictions, or applications where code density is an issue.
The key idea behind THUMB is that of a super-reduced instruction set. Essentially, the
ARM7TDMI-S processor has two instruction sets:

• The standard 32-bit ARM instruction set.
• A 16-bit THUMB instruction set.
The THUMB set’s 16-bit instruction length allows it to approach twice the density of
standard ARM code while retaining most of the ARM’s performance advantage over a
traditional 16-bit processor using 16-bit registers. This is possible because THUMB
code operates on the same 32-bit register set as ARM code.
THUMB code is able to provide up to 65% of the code size of ARM, and 160% of the
performance of an equivalent ARM processor connected to a 16-bit memory system.

The ARM7TDMI-S processor is described in detail in the ARM7TDMI-S Datasheet
that can be found on official ARM website.

© Koninklijke Philips Electronics N.V. 2005. All rights reserved.

User manual

Rev. 01 — 15 August 2005

5

UM10139

Philips Semiconductors
Volume 1

Chapter 1: Introductory information

1.7 On-chip Flash memory system
The LPC2141/2/4/6/8 incorporate a 32 kB, 64 kB, 128 kB, 256 kB, and 512 kB Flash
memory system respectively. This memory may be used for both code and data storage.
Programming of the Flash memory may be accomplished in several ways: over the serial
built-in JTAG interface, using In System Programming (ISP) and UART0, or by means of
In Application Programming (IAP) capabilities. The application program, using the IAP
functions, may also erase and/or program the Flash while the application is running,
allowing a great degree of flexibility for data storage field firmware upgrades, etc. When
the LPC2141/2/4/6/8 on-chip bootloader is used, 32 kB, 64 kB, 128 kB, 256 kB, and 500
kB of Flash memory is available for user code.
The LPC2141/2/4/6/8 Flash memory provides minimum of 100,000 erase/write cycles
and 20 years of data-retention.

1.8 On-chip Static RAM (SRAM)
On-chip Static RAM (SRAM) may be used for code and/or data storage. The on-chip
SRAM may be accessed as 8-bits, 16-bits, and 32-bits. The LPC2141/2/4/6/8
provide 8/16/32 kB of static RAM respectively.
The LPC2141/2/4/6/8 SRAM is designed to be accessed as a byte-addressed memory.
Word and halfword accesses to the memory ignore the alignment of the address and
access the naturally-aligned value that is addressed (so a memory access ignores
address bits 0 and 1 for word accesses, and ignores bit 0 for halfword accesses).
Therefore valid reads and writes require data accessed as halfwords to originate from
addresses with address line 0 being 0 (addresses ending with 0, 2, 4, 6, 8, A, C, and E
in hexadecimal notation) and data accessed as words to originate from addresses with
address lines 0 and 1 being 0 (addresses ending with 0, 4, 8, and C in hexadecimal
notation). This rule applies to both off and on-chip memory usage.
The SRAM controller incorporates a write-back buffer in order to prevent CPU stalls during
back-to-back writes. The write-back buffer always holds the last data sent by software to the
SRAM. This data is only written to the SRAM when another write is requested by software
(the data is only written to the SRAM when software does another write). If a chip reset
occurs, actual SRAM contents will not reflect the most recent write request (i.e. after a
"warm" chip reset, the SRAM does not reflect the last write operation). Any software that
checks SRAM contents after reset must take this into account. Two identical writes to a
location guarantee that the data will be present after a Reset. Alternatively, a dummy write
operation before entering idle or power-down mode will similarly guarantee that the last data
written will be present in SRAM after a subsequent Reset.

© Koninklijke Philips Electronics N.V. 2005. All rights reserved.

User manual

Rev. 01 — 15 August 2005

6

UM10139

Philips Semiconductors
Volume 1

Chapter 1: Introductory information

1.9 Block diagram

LPC2141/42/44/46/48
P0[31:28] and
P0[25:0]

TMS

(1)

TDI

(1)

TCK

(1)
TDO

TEST/DEBUG
INTERFACE
AHB BRID GE

FAST GENERAL

PLL0
system

ARM7TDMI-S

PURPOSE I/O

XTAL2
XTAL1
RST

(1)

EMULATION
TRACEMOD
ULE

TRST

(1)

SYSTEM
FUNCTIONS

clock

P1[31:16]

PLL1
VECTORED

USB
clock

ARM7 local bus

INTERRUPT
CONTROLLER

AMBA AHB
(Advanced High-performance Bus)
INTERNAL
SRAM
CONTROLLER

INTERNAL
FLASH
CONTROLLER

8/16/32 kB

32/64/128/256/512 kB

AHB TO VPB

VP
B

SRAM

FLASH

BRIDGE

DIVIDER
VPB (VLSI
peripheral bus)

EXTERNA
L
INTERRUPTS

EINT3 to EINT0

8 kB RAM

AHB

SHARED WITH
(3)

DECODER

USB DMA

D+
D−

USB 2.0 FULL-SPEED
DEVICE CONTROLLER
(3)
WITH DMA

UP_LED
CONNECT

V

BUS

4 × CAP0
4 × CAP1
8 × MAT0
8 × MAT1
AD0[7:6] and
AD0[4:1]

CAPTURE/COMPARE
(W/EXTERNAL CLOCK)
TIMER 0/TIMER 1

A/D CONVERTERS

SCL0, SCL1

2

I C-BUS SERIAL

INTERFACES 0 AND 1

SDA0, SDA1

SCK0, SCK1
MOSI0, MOSI1

SPI AND SSP

0 AND

(2)

AD1[7:0]

AOUT

1

(2)

SERIAL INTERFACES

MISO0, MISO1
SSEL0, SSEL1
TXD0, TXD1
RXD0, RXD1

(4)
D/A CONVERTER

UART0/UART1

(2)
(2)
DSR1 ,CTS1 ,
(2)
(2)
RTS1 , DTR1

(2)

P0[31:28] and
P0[25:0]
P1[31:16]

GENERAL
PURPOSE I/O

DCD1 ,RI1
RTXC1
REAL-TIME CLOCK

(2)

RTXC2

V
BAT

PWM6 to PWM0

PWM0

WATCHDOG
TIMER
SYSTEM
CONTROL
002aab560

(1) Pins shared with GPIO.
(2) LPCC2144/6/8 only.
(3) USB DMA controller with 8 kB of RAM accessible as general purpose RAM and/or DMA is available in LPC2146/8 only.
(4) LPC2142/4/6/8 only.

Fig 1. LPC2141/2/4/6/8 block diagram
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.

User manual

Rev. 01 — 15 August 2005

7

UM10139
Chapter 2: LPC2141/2/4/6/8 Memory Addressing
Rev. 01 — 15 August 2005 User manual

2.1 Memory maps
The LPC2141/2/4/6/8 incorporates several distinct memory regions, shown in the
following figures. Figure 2 shows the overall map of the entire address space from
the user program viewpoint following reset. The interrupt vector area supports
address remapping, which is described later in this section.

4.0 GB

0xFFFF FFFF

AHB PERIPHERALS
3.75 GB

0xF000 0000
VPB PERIPHERALS
0xE000 0000

3.5 GB
3.0 GB

0xC000 0000

RESERVED ADDRESS SPACE

2.0 GB
BOOT BLOCK
(12 kB REMAPPED FROM ON-CHIP FLASH MEMORY)

0x8000 0000
0x7FFF D000
0x7FFF CFFF

RESERVED ADDRESS SPACE
0x7FD0 2000
0x7FD0 1FFF

8 kB ON-CHIP USB DMA RAM (LPC2146/2148)
RESERVED ADDRESS SPACE
32 kB ON-CHIP STATIC RAM (LPC2146/2148)
16 kB ON-CHIP STATIC RAM (LPC2142/2144)
8 kB ON-CHIP STATIC RAM (LPC2141)
1.0 GB

0x7FD0 0000
0x7FCF FFFF

0x4000 8000
0x4000 7FFF
0x4000 4000
0x4000 3FFF
0x4000 2000
0x4000 1FFF
0x4000 0000
0x3FFF FFFF

RESERVED ADDRESS SPACE

0.0 GB

TOTAL OF 512 kB ON-CHIP NON-VOLATILE MEMORY
(LPC2148)
TOTAL OF 256 kB ON-CHIP NON-VOLATILE MEMORY
(LPC2146)
TOTAL OF 128 kB ON-CHIP NON-VOLATILE MEMORY
(LPC2144)
TOTAL OF 64 kB ON-CHIP NON-VOLATILE MEMORY
(LPC2142)
TOTAL OF 32 kB ON-CHIP NON-VOLATILE MEMORY
(LPC2141)

0x0008 0000
0x0007 FFFF
0x0004 0000
0x0003 FFFF
0x0002 0000
0x0001 FFFF
0x0001 0000
0x0000 FFFF
0x0000 8000
0x0000 7FFF
0x0000 0000

Fig 2. System memory map

© Koninklijke Philips Electronics N.V. 2005. All rights reserved.

User manual

Rev. 01 — 15 August 2005

8


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