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energies
Article

An Innovative Dual-Boost Nine-Level Inverter with
Low-Voltage Rating Switches
Meysam Saeedian 1 , Edris Pouresmaeil 1, * , Emad Samadaei 2 ,
Eduardo Manuel Godinho Rodrigues 3 , Radu Godina 4 and Mousa Marzband 5
1
2
3
4

5

*

Department of Electrical Engineering and Automation, Aalto University, 02150 Espoo, Finland;
meysam.saeedian@aalto.fi
Department of Electronics Design (EKS), Mid Sweden University, Holmgatan 10, 85170 Sundsvall, Sweden;
emad.samadaei@miun.se
Management and Production Technologies of Northern Aveiro—ESAN, Estrada do Cercal 449, Santiago de
Riba-Ul, 3720-509 Oliveira de Azeméis, Portugal; emgrodrigues@ua.pt
Research and Development Unit in Mechanical and Industrial Engineering (UNIDEMI), Department of
Mechanical and Industrial Engineering, Faculty of Science and Technology (FCT), New University of Lisbon,
2829-516 Caparica, Portugal; rd@ubi.pt
Department of Maths, Physics and Electrical Engineering, Faculty of Engineering and Environment,
Northumbria University, Newcastle upon Tyne NE1 8ST, UK; mousa.marzband@northumbria.ac.uk
Correspondence: edris.pouresmaeil@aalto.fi; Tel.: +358-505-984-479

Received: 3 December 2018; Accepted: 4 January 2019; Published: 9 January 2019




Abstract: This article presents an innovative switched-capacitor based nine-level inverter employing
single DC input for renewable and sustainable energy applications. The proposed configuration
generates a step-up bipolar output voltage without end-side H-bridge, and the employed capacitors
are charged in a self-balancing form. Applying low-voltage rated switches is another merit of the
proposed inverter, which leads to extensive reduction in total standing voltage. Thereby, switching
losses as well as inverter cost are reduced proportionally. Furthermore, the comparative analysis
against other state-of-the-art inverters depicts that the number of required power electronic devices
and implementation cost is reduced in the proposed structure. The working principle of the proposed
circuit along with its efficiency calculations and thermal modeling are elaborated in detail. In the
end, simulations and experimental tests are conducted to validate the flawless performance of the
proposed nine-level topology in power systems.
Keywords: power conversion; multilevel inverter; improved switched-capacitor module; multi
carrier based modulation

1. Introduction
In recent years, extensive research has been carried out on multilevel inverters (MLIs) due to their
potential in various industrial applications, particularly grid-connected renewable energy sources,
machine drives, and high-voltage direct current transmission systems. Improved output waveforms
quality, reduced device stress (dv/dt), and increased efficiency are some merits of the MLIs in
comparison with the standard two-level inverter [1–4]. The most popular traditional/basic multilevel
topologies are CHB, NPC, and FC, which have widely been put into commercial use in high/medium
voltage systems (above 3 kV). Nonetheless, high control/modulation technique complexity and
large power electronic device count (dc power supplies, semiconductors, and capacitors) are cited as
demerits of the aforementioned topologies [5–7].
To overcome these drawbacks, researchers and industrialists all around the world are contributing
to present innovative topologies with the ability to produce more voltage levels with reduced device
Energies 2019, 12, 207; doi:10.3390/en12020207

www.mdpi.com/journal/energies

Energies 2019, 12, 207

2 of 15

count and to further improve energy efficiency. Apart from that, it has tried to develop MLIs with
lower voltage-rating switches and to cope with the voltage unbalancing problem in NPC and FC. These
attempts lead not only to reducing filter requirement and simplicity, but also cost/volume reduction of
the conversion system [8–10].
Despite a plethora of multilevel topologies that have been presented, intensive effort has been
devoted to introduce promising topologies. For example, ref. [11,12] presented novel MLIs employing
the technique of switched-capacitor. Although a substantial reduction in the device count is achieved
in these topologies as compared to the conventional ones, they however require H-bridge circuits to
generate bipolar voltages. This weakness leads to a sharp increase in total standing voltage (TSV)
and thereupon switches cost. A single source nine-level (9 L) inverter has been proposed in [13],
which applies semiconductors with the same Peak inverse voltage (PIV) equal to input voltage level.
Nevertheless, this topology utilizes numerous insulated-gate bipolar transistors (IGBTs) and gate
drivers, which enlarge the system. A hybrid cascaded MLI with improved symmetrical sub-module
was introduced in [14]. It employs four dc sources and ten switches with high PIVs to produce a 9 L
voltage waveform. Furthermore, [15] introduced a single source inverter which is comprised of an
H-bridge inverter and two switched-capacitor modules. It employs sixteen IGBTs with low voltage
ratings for generating a 7 L output voltage. Yet, these presented MLIs in the literature suffer from
either a large number of circuit elements or relatively high PIVs.
In summary, the main contribution of this paper is the development of a modified 9 L inverter
for single phase systems, which is superior to all the earlier topologies. The switches employed in
the proposed configuration enjoy low PIVs. At the same time, a further reduction in device count
and implementation cost is attained in the proposed circuit compared to the traditional/cutting-edge
ones. Moreover, there is no difficulty in the capacitors’ charging process since the inverter is inherently
self-balanced. Due to the voltage boosting capability, this inverter is proposed for grid-connected
renewable energy sources (such as solar and wind farms), uninterruptible power supplies, and
electric vehicles in which low input DC voltages are required to be boosted to an acceptable range for
these systems.
The rest of this article is structured into five sections. Following the introduction, Section 2
presents the operating principle and a detailed comparative study of the proposed topology in order to
demonstrate the superiority of the proposed inverter against newest 9 L topologies. Section 3 describes
PWM strategy applied to the proposed inverter. Efficiency calculations and thermal analysis are carried
out in Section 4. The simulation and experimental results are brought in Section 5 in order to prove
the feasibility and effectiveness of the presented topology. Eventually, conclusions are presented in
Section 6.
2. Analysis of the Proposed Nine-Level Inverter
2.1. Circuit Description
Figure 1 depicts the proposed switched-capacitor based inverter with the potential of generating
a 9 L staircase waveform (±2VIN , ±3VIN /2, ±VIN , ±VIN /2 and 0). As demonstrated in Figure 1,
it comprises twelve power switches, two capacitors (C1 , C2 ), and only one input DC source with the
advantage of regenerative capability. The output voltage can be boosted up to 2VIN by connecting the
input source with pre-charged capacitors in series. It should be underscored that the blocking voltage
of all switches employed in the proposed inverter is equal to the input DC source (i.e., VIN ), with the
exception of S7 , S8, and S12 which block only half the VIN . In other words, it generates a bipolar output
voltage without using end-side H-bridge. This ability is considered a beneficial feature of the proposed
circuit since the lower switch voltage rating, the cheaper switch.
The working principle of the proposed inverter is illustrated in Figure 2. As can be observed,
C1 and C2 are charged up to VIN /2 by turning S3 and S4 on during 0 and ±1VIN levels. Then, the
capacitors are connected in parallel at ±VIN /2 and ±3VIN /2 levels. Thereby, the voltage across them

Energies 2019, 12, x FOR PEER REVIEW

Energies 2019, 12, 207

3 of 15

S1

S3

S5

C1

S7

3 of 15

S9

is balanced. Finally, they areAdischarged across the load during ±VIN /2 and
B ±2VIN levels. Relying on
VIN
S11
S12
this
simple
switching
plan,
the
proposed
inverter
does
not
require
any
external
balancer circuit.3 of 15
Energies 2019, 12, x FOR PEER REVIEW

S8

S2
S1

S4
S3
ILoad

A

+

S11VLoad=VA-VB

S10
S9

C1

LS7

R

VIN

C2

S6
S5
-

B

S12

Figure 1. The proposed 9 L topology.

S8

C2

2 proposed
S4 inverter
S6 is illustrated inSFigure
10
The working principle of S
the
2. As can be observed, C1
and C2 are charged up to VIN/2 by turning S3 and S4 on during 0 and ±1VIN levels. Then, the capacitors
R
L
ILoad
are connected in parallel at ±VIN/2 and ±3V+ IN/2 levels. Thereby,
the voltage across them is balanced.
Load=VA-V
Finally, they are discharged across the loadVduring
±VBIN/2 and ±2VIN levels. Relying on this simple
switching plan, the proposed inverter
not
require99any
external balancer circuit.
Figure
1.
proposed
LL topology.
Figuredoes
1. The
The
proposed
topology.

working
in Figure 2. As can be observed, C1
SThe
1
S3
S5 principle of
S9 the proposed
S1
Sinverter
3
S5 is illustrated
S9
S1
S3
S5
S9
C1 0 and ±1VIN levels. Then, the capacitors
C1
and C2 are chargedS7up to CV1 IN/2 by turning S3 and S4 on
during
S7
S7
are
connected
in parallel at ±VIN/2 Aand ±3V
IN/2 levels. Thereby, the voltage across them is balanced.
A
V
V
V
S11
S12
B
S11
B A
S11
S12
B
S12
Finally, they are discharged across the load during ±VIN/2 and ±2VIN levels. Relying on this simple
S
8
S8
S8
C2
switching plan, the proposed
inverter does not require anyC2external balancer circuit.
C2
IN

S2

S4

S6

S1
S1

S3
S3

(a)
S5
S5 S7
S7

A
A

A

IN

S11
S11

VIN
VIN

S2
S2

S4
S4

S8
S6 S 8
S6
(a)

S1

S3

S5
(d)

S1 VIN

S3S11

S7

S5
S7
S8

A S2 VIN S4 S11

S6
S8

S2

S4

S6
(d)

S1

S3

S(g)
5
S7

A

S2

S4

S6

S10

S2

S4

S6

S1

S3

(b)
S5

S9

S1

S3

(c)
S5

S10

S9
C1
S9
C1
S12
B A
S12
B
A
C2
S10
C2
S10

C1

S9

S12 S9
C1

B

C2
S12 S10

B

C2

C1

S10
S9

IN

S1
VIN

S3
S11

S5

S7
S8

S11

VIN

S2

S4

S6

S2

S4

S6
(b)

S1

S3

S(e)
5

S1

A

S3

A

S5

S11

VIN

S8

S7
S7

S8

S11

VIN

S7

S2

S4

S6

S2

S4

S6
(e)

S1

S3

S5
(h)

S8

S7

C1

C1
S12

S9

S1

B

S12
C2
S10
C2
S10

C1
C1
S12

VIN

B A

S9

S5

S8

S4

S6

S2

S4

S6
(c)

S1

S3

S(f)
5

VIN

BA

S3
S11

S5

S8

S7

S7
S8

S11

VIN

S7

S7

S11

VIN

B A

S9

S3
S11

S2

S1

S9

S12
C2
S10
C2
S10

C1

A

S10

S2

S4

S6

S2

S4

S6
(f)

S1

S3

S5
(i)

S8

S7

C1

C1
S12
S12
C2
C2

C1

S9

S9
B

B
S10

S10
S9

S9

C1
S12

B

S12
C2
S10
C2
S10

C1

S9

Figure 2.
2. Switching
Switching states
states of
of the
the
proposed
inverter,(a)
(a)+2V
+2VIN
IN,, (b)
(b) +3V
+3VIN
IN/2,
ININ
, (d)
IN/2,
(e) (e)
0; (f)
Figure
inverter,
/2,(c)
(c)V+V
+V
, (d)+V+V
0;
IN /2,
A proposed
V
S11
S12
BA
S11
S12
V
S
11
S
12
B
IN/2,
IN,−
(h)
−3V
IN/2,
(i)IN
−2V
. −2VIN .
−V−
(f)
VIN(g)
/2,−V
(g)
VIN
, (h)
−3V
/2,IN(i)
IN

B

IN

B

IN

S8

C2
2.2.
Assessment
2.2.SComparative
Comparative
2
S4
S6 AssessmentS10

S8

S2

S4

S6

C2

S8

S10

S2

S4

S6

C2

S10

Table
the
other
in
Table 11 compares
compares
the presented
presented circuit
circuit with
with(h)
other recently-introduced
recently-introduced topologies
topologies
in terms
terms of
of the
the
(g)
(i)
number
of
required
semiconductors/DC
sources
and
switches
voltage
rating.
As
observed
from
number of required semiconductors/DC sources and switches voltage rating. As observed from the
the
2. Switching
states
of
the
proposed
(a) number
+2Vof
IN, (b)of
+3V
IN/2, (c) +V
IN, (d)
+VIN
/2, (e)compared
0; (f)to the
table,
ref.
the proposed
circuit
employs
the least
switches
and
capacitors
table,Figure
[14] [14]
the
proposed
circuit
employs
theinverter,
least
number
switches
and capacitors
compared
IN/2, (g)
−VINThese
, (h) −3V
IN/2, (i) −2VIN. result in simpler control and a higher degree of compactness.
to
the−Vones.
other
ones.
minimizations
other
These
minimizations
result in simpler control and a higher degree of compactness. Apart
Apart
from
this,
the
table
a fourfold
increase
in the number
of required
DC supplies
power supplies
from this, the table depictsdepicts
a fourfold
increase
in the number
of required
DC power
for [14]
2.2.
Comparative
Assessment
for
[14]
and
conventional
CHB,
while
the
others
and
proposed
inverter
utilize
only
one
DC
source.
and conventional CHB, while the others and proposed inverter utilize only one DC source.
Applying
switches
with
lower
is
aa distinct
advantage
inverter.
In
other
Table
1 compares
the
presented
circuit
with
other recently-introduced
topologies
in terms
the
Applying
switches
with
lower PIV
PIV
is also
also
distinct
advantage of
of the
the proposed
proposed
inverter.
Inof
other
words,
it
enjoys
the
lowest
level
of
TSV.
To
prove
this,
the
number
of
employed
IGBTs
with
the
number
required
semiconductors/DC
sources
voltage
rating. AsIGBTs
observed
the
words, itofenjoys
the lowest
level of TSV. To
proveand
this,switches
the number
of employed
with from
the same
same
voltage
rating
for each structure
is presented
in number
the following
table.and
For capacitors
instance, the
proposed
9L
table,
[14]
the proposed
circuit employs
the least
of switches
compared
to the

other ones. These minimizations result in simpler control and a higher degree of compactness. Apart
from this, the table depicts a fourfold increase in the number of required DC power supplies for [14]
and conventional CHB, while the others and proposed inverter utilize only one DC source.
Applying switches with lower PIV is also a distinct advantage of the proposed inverter. In other
words, it enjoys the lowest level of TSV. To prove this, the number of employed IGBTs with the same

Energies 2019, 12, 207

4 of 15

inverter needs nine and three switches with the PIV of 1VIN and VIN /2 respectively, while [13] requires
nineteen IGBTs with the voltage ratings of VIN . Thereby, the proposed inverter can be an acceptable
alternative to the topologies listed in Table 1.
Table 1. Comparison of the proposed topology with other recently presented inverters.
Comparison Item

CHB (Con.)

[11] (2010)

[12] (2017)

[13] (2018)

[14] (2018)

[15] (2018)

Level
Switch
Capacitor
DC source

9
16
4

9
13
3
1

9
12
4
1

9
19
3
1

9
10
4

7
16
2
1

9
12
2
1

Proposed
8M * + 1
12M
2M
M

N * × PIV

16 × 1VIN

4 × 4VIN
9 × 1VIN

4 × 4VIN
8 × 1VIN

19 × 1VIN

4 × 4VIN
2 × 3VIN
4 × 1VIN

16 × 1VIN

9 × VIN
3 × VIN /2

9M × VIN
3M × VIN /2

TSV

16VIN

25VIN

24VIN

19VIN

26VIN

16VIN

21VIN /2

M × (21VIN /2)

M *: Number of cascaded modules.

Furthermore, the single-source topologies are also compared in terms of total implementation cost
(see Table 2). It should be noted that CHB and [14] are not considered in the cost-comparative analysis
since they require four DC power supplies. For a fair comparison, power rating (i.e., volt/ampere
rating) of all the MLIs are assumed to be equal to 5 kW/30.7 A. Moreover, a 50% voltage rating margin
is considered for the selection of switches and capacitors. It is observed from Table 2 that the proposed
inverter requires the least implementation cost compared to the other ones.
Table 2. Price Comparison of the Single-Source MLIs.
Part

Part Number

Voltage Rating
(V)

Unit Price *
(€)

[11]

[12]

[13]

[15]

Proposed

MOSFETs

STW40NF20
SUP40N25-60-E3
FQL40N50
SIHG47N60AEFGE3

200
250
450
600

3.53
4.43
7.73
7.82

9
4

8
4

19
-

16
-

3
9
-

Capacitors

E32D151HPN472TEE3M
B43713F2478M000
ALS31A472NF350

150
250
350

23.00
39.39
48.83

3
-

2
2

4
-

2
-

2
-

Gate driver

IRS21271SPBF

-

1.34

13

12

19

14

12

149.47

219.26

184.53

168.42

112.54

Total cost (€)

* Source: www.mouser.com.

3. Multicarrier PWM Strategy
Therein, phase disposition PWM technique is applied to control each IGBT of the proposed
topology. To do this, eight triangular carriers (Vt1 to Vt8 ) arranged with shifts in amplitudes are
required (see Figure 3a). It should be noted that they are the same in amplitude (At ), frequency (ft ) and
phase [16,17]. The carriers are compared to a reference waveform (Vref ) which results in generating
appropriate fire pulses for all switches. For instance, S11 is turned on when Vref > Vt1 or Vt2 < Vref < Vt1
or Vt8 < Vref < Vt7 or Vref <Vt8 . In other words, S11 must be turned on when S1 : ON, S4 : ON, S3 : OFF
(or S2 : ON, S3 : ON, S4 : OFF), which can be observed in Figure 2. Similarly, S12 is turned on when Vref >
Vt1 or Vt3 < Vref < Vt2 or Vt5 < Vref < Vt4 or Vt7 < Vref < Vt6 or Vref < Vt8 . In other words, S12 must be
turned on when S7 and S8 are OFF (see Figure 2). Further clarification concerning switching strategy is
brought up in Figure 3b and Table 3.

Energies 2019, 12, 207

5 of 15

Energies 2019, 12, x FOR PEER REVIEW

5 of 15

Vref

Are f

4At

Vt1

3At

Vt2

2At

Vt3

At

Vt4
Vt5

-At

Vt6

-2At

Vt7

-3At

Vt8

-4At

2VIN
3VIN/2
VIN
VIN/2
0
-VIN/2
-VIN
-3VIN/2
-2VIN
0 t1 t2 t3

t4 t5 t6 π t7 t8 t9

t10 t1 1 t12 2π

(a)
S12
N OT

N OT

Vt1

+
-

Vt2

+
-

Vt3

+
-

Vt4

+
+
-

Vt6

+
-

AND

S 7 & S8

OR

AND

AND

OR

S6

OR

S5

OR

S4

AND

S1
N OT

Vt5

N OT

Vref

N OT

AND

S2

N OT

N OT

AND
OR

S3

AND

Vt7

+
-

Vt8

+
-

N OT

AND

OR

N OT

S11

N OT

S10
N OT

S9

(b)
Figure3.3.(a)
(a) PWM
PWM technique,
technique, (b)
Figure
(b)Logic
Logicschematic.
schematic.

Table
IGBTs for
for Each
EachLevel.
Level.
Table3.
3. On-State
On-State IGBTs
Relationship
between
Carriers
ON-StateIGBTs
IGBTs Levels
Relationship
between
the the
Carriers
and and
Vref Vref ON-State
Levels
Vt1
Vref V
>refV>
t1
t2 < V
ref
<t1 Vt1
Vt2 <VV
<
V
ref
t3 < V
Vt3 <VV
t2 Vt2
ref <refV<
t4 ref
<V
Vt4 <VV
<refV<t3 Vt3
Vt5 <VV
<refV<t4 Vt4
t5 ref
<V
Vt6 <VV
<refV<t5 Vt5
t6 ref
<V
Vt7 <VV
<refV<t6 Vt6
t7 ref
<V
Vt8 < Vref < Vt7
Vt8 < Vref < Vt7
Vref < Vt8
Vref < Vt8

4-S5-S10-S11-S12
S1S
-S1-S
4 -S5 -S10 -S11 -S12
4-S5-S7-S8-S10-S11
S1S-S1-S
-S
4 5 -S7 -S8 -S10 -S11
3-S
4-S-S
6-S10
-S1212
S1S-S1-S
3 -S
4 -S
5 5-S
6 -S
10 -S
3-S
5-S
7-S
8-S
S1S-S1-S
3 -S
5 -S
7 -S
8 -S
1010
S2S-S2-S
-S-S
3-S
4-S
5-S
6-S
3 -S
4 -S
5 -S
6 -S
1010
1212
S2S-S2-S
4 -S
6 -S
7 -S
8 -S
99
4-S
6-S
7-S
8-S
S2S-S2-S
3 -S
4 -S
5 -S
6 -S
9 -S
1212
3-S
4-S
5-S
6-S
9-S
S2 -S3 -S6 -S7 -S8 -S9 -S11
S2-S3-S6-S7-S8-S9-S11
S2 -S3 -S6 -S9 -S11 -S12

S2-S3-S6-S9-S11-S12

+4V
IN
+4V
IN
+3V
IN
+3V
IN
+2V
IN
+2V
IN
+1V
IN IN
+1V
0 0
−1V
−1V
IN IN
−2V
−2V
IN IN
−3V
IN
−3V
IN
−4VIN
−4VIN

Energies 2019, 12, 207

6 of 15

4. Loss Distribution and Thermal Modeling
4.1. Power Loss Analysis
The power loss for a multilevel inverter is composed of three parts including PC , PS and PR which
are elaborated as follows:
4.1.1. Conduction Loss (PC )
PC is caused by parasitic resistance (i.e., ON-state resistance of the switch (RS ) and its parallel
diode (RD ), capacitor internal resistance (RC )) involved in the current paths [18]. Table 4 shows the
equivalent value of the parasitic resistance (Req ) existing in each voltage level. It should be noted that
in the present work RS , RD, and RC are considered equal to 0.27 Ω, 0.05 Ω, and 0.03 Ω, respectively.
Table 4. Req in Each Step.
Output Level

Req (Ω)

0
±VIN /2
±VIN
±3VIN /2
±2VIN

2RS + 2RD = 0.64
3RS + 2RD + RC = 0.94
3RS + RD = 0.86
5RS + RD + RC = 1.43
6RS + 2RC = 1.68

If |Vref | < At , the output voltage switches between 0 and +VIN /2 (see Figure 3a). Consequently,
the output current passes through two switches and two diodes (three switches, two diodes, and one
capacitor) during 0 (+VIN /2) level, as depicted in Table 4. In this case, the energy dissipated within
0 < t < t1 (t6 < t < t7 or t12 < t < 2π) is attained by Equation (1) in which At , Aref , and fref are considered
equal to 0.25, 0.9, and 50 Hz, respectively [18]. Moreover, t1 is calculated as follows:
E0&VI N /2 =

Rt1h
0



i2
A sin(2π f t)
ILoad sin 2π f re f t
× (3RS + 2R D + RC ) re f At re f +(2RS + 2R D ) 1 −

Are f sin(2π f re f t)
At


dt

(1)

= 2.04 × 10−5 × ( Pout/VI N )2

t1 =

sin−1 ( At/Are f )
sin−1 (0.25/0.9)
=
= 9 × 10−4 sec.
2π f re f
100π

(2)

Similarly, the energy losses that occurred in other time intervals are calculated by Equations (3)–(8).
EVI N /2 &VI N =

Rt2h
t1



i2
A sin(2π f re f t)− At
ILoad sin 2π f re f t
× (3RS + R D ) re f
+(
3R
+
2R
+
R
1−
)
D
S
C
At

= 2.03 × 10−4 × ( Pout/VI N )

t2 =
EVI N &3VI N /2 =

Rt3h
t2

Rt4h
t3

dt

sin−1 (2At/Are f )
sin−1 (0.5/0.9)
=
= 1.87 × 10−3 sec.
2π f re f
100π

=

E3VI N /2 &2VI N =



7.2 × 10−4

× ( Pout/VI N )

(4)
Are f sin(2π f re f t)−2At
At


dt



i2
A sin(2π f re f t)−3At
ILoad sin 2π f re f t
× (6RS + 2RC ) re f
+(
5R
+
R
+
R
1−
)
D
C
S
At

= 0.0051 × ( Pout/VI N )

(5)

2

sin−1 (3At/Are f )
sin−1 (0.75/0.9)
=
= 3.1 × 10−3 sec.
2π f re f
100π

2

(3)

2



i2
A sin(2π f re f t)−2At
ILoad sin 2π f re f t
× (5RS + R D + RC ) re f
+(3RS + R D ) 1 −
At

t3 =

Are f sin(2π f re f t)− At
At

(6)
Are f sin(2π f re f t)−3At
At


dt

(7)

Energies 2019, 12, 207

7 of 15

t4 =

π − sin−1 (3At/Are f )
π − sin−1 (0.75/0.9)
= 6.86 × 10−3 sec.
=
2π f re f
100π

(8)

Due to quarter-wave symmetry of the output voltage, the total conduction loss for the proposed
9 L topology is:

PC = 4E0 &VI N /2 + 4EVI N /2 &VI N + 4EVI N &3VI N /2 + 2E3VI N /2 &2VI N × f re f = 0.69 × ( Pout/VI N )2

(9)

4.1.2. Switching Loss (PS )
The overlap of switch voltage and current during rise and fall times (i.e., ton and toff ) leads to PS ,
which is highly proportional to the fS . The turn-on and turn-off power loss of the switch S are attained
by [19]:
on

Zton
Zton
IS
VS
1
t

(10)
PS, on = f S vS (t) iS (s) dt = f S
(t − ton ) dt = f S VS ISon ton
ton
ton
6
0

0

t

PS,o f f = f S

Zo f f

t

vS (t) iS (t) dt = f S

0
on

Zo f f

VS
t
to f f

0

!

of f

I
− S
t − to f f
to f f

!
dt =

1
of f
f V I t
6 S S S of f

(11)

off )

In which IS (IS is the switch current after (before) turning on (off). Considering ton = toff =
58 ns and ft = 4 kHz, PS for all the switches is obtained as follows:
PSj,on = PSj,o f f =

1
6

× 12 × 4 × 103 × VI N ×

ILoad
π

× 58 × 10−9 = 6.15 × 10−6 × Pout , j = 1, 2, 9, 10, 11 (12)

1
I
× 4 × 103 × VI N × Load × 58 × 10−9 = 12.3 × 10−6 × Pout , j = 3, 4, 5, 6
6
π
V
I
1 1
PSj,on = PSj,o f f = × × 4 × 103 × I N × Load × 58 × 10−9 = 3.07 × 10−6 × Pout , j = 7, 8
6 2
2
π
1 1
V
I
PS12,on = PS12,o f f = × × 4 × 103 × I N × Load × 58 × 10−9 = 3.07 × 10−6 × Pout
6 2
2
π
PSj,on = PSj,o f f =

(13)
(14)
(15)

Consequently, the total switching loss for the presented 9 L inverter is calculated by:
Nswitch

PS =




PSj, ON + PSj ,OFF = 178 × 10−6 × Pout

(16)

j =1

4.1.3. Power Loss Generated by Capacitor Voltage Ripple (PR )
PR is due to the voltage difference between the capacitor and input DC source during the charging
periods. Generally, the maximum discharging value of each capacitor in a switched-capacitor circuit is
attained by [13,18]:
∆QC =

Ztd

ILoad Sin(2π f re f t)dt

(17)

tc

where [tc , td ] is the discharging interval of each capacitor. According to Figures 2a and 3a, the maximum
discharging period of C1 (or C2 ) is equal to [t3 , t4 ]. Thus, considering maximum acceptable voltage
drop across C1 (or C2 ) equal to ∆Vripple , the capacitance of each capacitor is calculated by [13,18]:
C≥

∆QC
∆Vripple × 0.5VI N

(18)

where [tc, td] is the discharging interval of each capacitor. According to Figures 2a and 3a, the
maximum discharging period of C1 (or C2) is equal to [t3, t4]. Thus, considering maximum acceptable
voltage drop across C1 (or C2) equal to ΔVripple, the capacitance of each capacitor is calculated by
[13,18]:

Energies 2019, 12, 207

8 of 15

C≥

Δ QC

(18)

ΔV ripple × 0.5V IN

For example, considering Pout = 1.4 kW (ILoad = 7 A, VIN =200 V) and ∆Vripple = 10%, the capacitances
(ILoad = 7 A, VIN=200 V) and ΔVripple = 10%, the capacitances
For
example,
considering
Pout = 1.4askW
for the
proposed
inverter
are obtained
follows:
for the proposed inverter are obtained as follows:
0.00686
R 0.00686
7 × Sin(100πt)dt
7 × Sin( 100π t )dt
0.024
0.0031 
(19)
0.024
C1 = CC2 =
=
= 2400 µF
(19)
0.0031
=
C
=
=
1
2
0.1 × 100
10= 2400 μ F
0.1 × 100

10

ItItalso
ININ/2
alsoshould
shouldbe
benoted
notedthat
thatnominal
nominalvoltage
voltageofofthe
thecapacitors
capacitorsisisequal
equaltotoVV
/2 (see
(see Figure
Figure 2).
2).
Consequently,
P
for
the
proposed
topology
is
attained
as
follows:
Consequently, PRR for the proposed topology is attained as follows:
!

2
0.00686
2
2
R
f
 0.00686
 = 0.088 × ∆V
2
PRP== re2ffref ∑ Ci C
∆Vripple
×
0.5V
=
50
×
I
sin
(
100πt
)
dt
×
∆V
×
0.5V
IN
I Loadsin(100π t )dt × ΔVripple× 0.5V I N = 0.088 × ΔV ripple
ΔV × 0.5V
= 50 ×
× P × Pout
R

2  
i =1

i =1

i

(

ripple

IN

)

 0.0031

 0.0031




Load

ripple

IN




ripple

out

(20)
(20)

Therefore,
Therefore,considering
consideringEquations
Equations(9),
(9),(16),
(16),and
and(20),
(20),the
theefficiency
efficiencyisiscalculated
calculatedby
byEquation
Equation(21).
(21).
PoutP
PPoutout
η = η = out
==
Pin P Pout
PC++PP+
S+
P +
P PR
+P
in

out

C

S

(21)
(21)

R

Theoretical
Theoreticalefficiency
efficiencyof
ofthe
theproposed
proposedinverter
inverterhas
hasbeen
beencalculated
calculatedat
atdifferent
differentoutput
outputpower
powerand
and
presented
in
Figure
4.
It
is
observed
that
there
is
a
marked
rise
in
the
efficiency
by
increasing
presented in Figure 4. It is observed that there is a marked rise in the efficiency by increasing the
the
output
outputpower.
power.
100
98
EFFICIENCY (%)

96
94
92
90
88
86
84
0

250

500

750 1000 1250 1500 1750 2000 2250
POUT (W)

Figure4.4. Inverter
Inverter efficiency
efficiencyat
atdifferent
differentpower
poweroutput.
output.
Figure

4.2.
4.2.Thermal
ThermalModel
Model
Heat
Heatdistribution
distribution through
throughsemiconductor
semiconductor components
components is
is caused
caused by
by power
power loss,
loss,which
whichleads
leadsto
to
an
increasing
of
T
[20].
This
temperature,
for
safety
reasons,
should
be
monitored
and
kept
within
j
an increasing of Tj [20]. This temperature, for safety reasons, should be monitored and kept withinaa
specified
operation.
Figure
5a 5a
illustrates
thethe
thermal
model
implemented
for
specifiedrange
rangeduring
duringthe
theinverter
inverter
operation.
Figure
illustrates
thermal
model
implemented
afor
single
semiconductor,
in
which
the
thermal
impedance
between
junction
and
case
(Z
)
is
considered
th
a single semiconductor, in which the thermal impedance between junction and
case (Zth) is
aconsidered
four-layer afoster
network
(see
Figure
5b)
[21,22].
It
should
be
noted
that
Z
and
Z
are
the
thermal
c
s
four-layer foster network (see Figure 5b) [21,22]. It should be noted that Zc and
Zs are
impedances
from
the
case
to
the
heat
sink
and
from
the
heat
sink
to
the
ambient,
respectively.
These
the thermal impedances from the case to the heat sink and from the heat sink to the ambient,
are
found on the
manufacturer
datasheet.
respectively.
These
are found on
the manufacturer datasheet.

Energies 2019,
2019, 12, x
207
Energies
Energies 2019,12,
12, xFOR
FORPEER
PEERREVIEW
REVIEW

TTj j

of 15
15
999of
of 15

ZZthth

TTcc

ZZcc

TTss

Sem
Semiconductor
iconductor

TTaa

CCss

CCthth

ΔP
ΔP

ZZss

Sem
HeatSink
Sink
Semiconductor
iconductor Heat
Case
Case
(a)
(a)

RRth1
th1

RRth2
th2

RRth3
th3

RRth4
th4

CCth1
th1

CCth2
CCth3
th2
th3
ZZthth

CCth4
th4

ΔP
ΔP

TTj j

TTaa

TTcc

(b)
(b)

Figure
5.5.(a)
model;
(b)
foster
network
of
ZZth
th..
Figure
(a)
Semiconductor
thermal
Figure5.
(a)Semiconductor
Semiconductorthermal
thermalmodel;
model;(b)
(b)foster
fosternetwork
networkof
ofZ
th.

yields
the
junction
Modelling
junction
Modellingloss
lossdissipation
dissipationof
ofthe
theproposed
proposed99LLinverter
inverterin
inMATLAB/Simulink
MATLAB/Simulinkyields
yieldsthe
the
junction

devices
[23–25].
T
is
C
temperature
of
the
power
electronic
Herein,
is
considered
equal
to
40
°C
and
a
temperature of the power electronic devices [23–25]. Herein, Ta is considered equal to 40 °C andthe
the
PM75CLA060
PM75CLA060switch
switchproduced
producedby
byMitsubishi
MitsubishiElectric
Electricisischosen
chosenininthe
thethermal
thermalestimation.
estimation.
estimated
of
some
power
switches
employed
in
the
proposed
inverter
at
The
Theestimated
estimatedTTjj jof
ofsome
somepower
powerswitches
switchesemployed
employedin
inthe
theproposed
proposedinverter
inverterat
at20
20kW
kWoutput
output
◦ C),
in
Figure
6.
can
be
observed
that
S
has
the
lowest
(approximately
43.9
power
is
illustrated
It
12 has
the
lowest
T
jj (approximately
43.9
12
power is illustrated in Figure 6. It can be observed that S12 has the lowest Tj (approximately 43.9°C),
°C),

C for
while
11..
whilethis
thistemperature
temperatureapproaches
approaches46.7
46.7°C
°C
forSS11
11.
j, S1
TT
j, S1

45
45
44.5
44.5
44
44

j, S9
TT
j, S9

45
45
44.5
44.5

j, S11
TT
j, S11

44
44

47
47

46.5
46.5
46
46

j, S12
TT
j, S12

44.5
44.5
44
44

43.5
43.54

4

4.1
4.1

4.2
4.2

4.3
4.3

4.4
4.4

4.5
4.5

Time (sec)
Time (sec)

4.6
4.6

4.7
4.7

4.8
4.8

4.9
4.9

5

5

Figure
The
j at 20 kW output power.
Figure6.
Theestimated
estimatedT
at 20
20 kW
kW output
output power.
power.
Figure
6.6.The
estimated
TTj j at

5. Simulation and Experimental Results
Simulations have been conducted in MATLAB for steady-state and transient modes, as presented
below. Figure 7 shows the inverter output voltage/current and capacitors voltage at resistive-inductive
load (ft = 4 kHz, C1 = C2 = 2300 µF, R = 100 Ω, L = 100 mH). These results confirm the flawless
performance and self-balanced ability of the presented 9 L inverter. Moreover, the value of the input
DC source is selected at 200 V. Thus, the capacitors and output voltages reach 100 V and 400 V,

Energies 2019, 12, 207

10 of 15

respectively.
ThePEER
proposed
topology has also been simulated under step change in the load, and the
Energies
2019, 12, x FOR
REVIEW
10 of 15
results are presented in Figure 8. As can be observed, the voltage ripple across the capacitors rises
promptly from
3.5% to 7.2% byResults
decreasing the load impedance. Once again, these figures verify the
5. Simulation
and Experimental
inherent capacitor voltage balancing ability during inverter operation.
Simulations
have the
been
conducted
in across
MATLAB
steady-state
and transient
modes, as
Figure 9 shows
voltage
waveforms
some for
power
switches employed
in the proposed
presented
below.
Figure
73 ,shows
inverter
and capacitors
voltage
topology.
It is clear
that S
S5, and the
S11 (also
S1 , S2 ,output
S4 , S6 , S9voltage/current
and S10 ) must withstand
voltages equal
to at
resistive-inductive
load(i.e.,
(ft =200
4 kHz,
C1 = switches
C2 = 2300
= 100
L = 100block
mH).
These equal
results
the input DC source
V). Other
(S7µF,
, S8 R
and
S12 ),Ω,
however,
voltages
to confirm
half
the flawless
and100
self-balanced
ability
oftopologies
the presented
L inverter.
Moreover,
thethe
value
the inputperformance
DC source (i.e.,
V). To sum up,
unlike
with 9end
side H-bridge,
none of
required
foristhe
proposed
inverter
tolerate
voltagevoltages
(i.e., 400 V).
of theswitches
input DC
source
selected
at 200
V. Thus,
themaximum
capacitorsoutput
and output
reach 100 V and
Furthermore,The
the effect
of different
modulation
indexes
switching
frequencies
on the operation
400 V, respectively.
proposed
topology
has also
beenand
simulated
under
step change
in the load,
of
the
proposed
inverter
is
shown
in
Figure
10.
It
is
observed
that
the
inverter
output
voltage
has
and the results are presented in Figure 8. As can be observed, the voltage ripple across the capacitors
lower THD at higher modulation index (and higher switching frequency). Moreover, the fundamental
rises promptly from 3.5% to 7.2% by decreasing the load impedance. Once again, these figures verify
component of output voltage is decreased at lower modulation index.

the inherent capacitor voltage balancing ability during inverter operation.
400

modulation index=0.9

VLoad (V)

200
VIN

0
-200
-400
4

ILoad (A)

2
0
-2
-4

8

IInput (A)

6
4
2

VC1 (V)

0

100
98

VC2 (V)

96
0 96

0 97

0 98

0 99

1

0.98

0.99

1

100
98
96
0.96

0.97

Time (sec)

Figure
7. Operation
modelunder
underconstant
constant
load.
Figure
7. Operationofofthe
thepresented
presented model
load.

400

VLoad (V)

200
0

Energies 2019, 12, 207

11 of 15

-200 REVIEW
Energies 2019, 12, x FOR PEER

11 of 15

-400
400

VLoad (V)
ILoad (A)

8
200

Load reduction at VLoad=0

4
0

0
-200
-4
-400
-88

ILoad I(A) (A)
Load

84

R=100 , L=0.1 H

R=50 , L=0.05 H

Load reduction at VLoad=0
Load reduction at VLoad=2VIN

40
0

-4
R=100 , L=0.1 H

-4

-8

-88
08

R=50 , L=0.05 H

09

1

11

-8
08

09

1

11

90
0.8
95

0.9

1

1.1

Load reduction at VLoad=2VIN

V (V)
ILoadC1(A)

100
4
95

0

90

-4

VC1 (V) VC2 (V)

100

95
100

1.2

Time (sec)

90

Figure 8. Operation of the presented model under sudden load reduction.
VC2 (V)

100

Figure 9 shows the voltage waveforms across some power switches employed in the proposed
95
topology. It is clear that S3, S5, and S11 (also S1, S2, S4, S6, S9 and S10) must withstand voltages equal to
90
the input DC source (i.e.,
block voltages
equal to half
0.8 200 V). Other
0.9 switches (S7, S
1 8 and S12), however,
1.1
1.2
Time (sec)
the input DC source (i.e., 100 V). To sum up, unlike topologies with end side H-bridge, none of the
8.8.proposed
Operation
model
undersudden
sudden
load
reduction.
switches requiredFigure
for
the
inverter
tolerate
maximum
output
voltage
(i.e., 400 V).
Figure
Operationof
of the
the presented
presented
model
under
load
reduction.

VS3 & VS5

Figure 9 shows200the voltage waveforms across some power switches employed in the proposed
topology. It is clear that S3, S5, and S11 (also S1, S2, S4, S6, S9 and S10) must withstand voltages equal to
the input DC source (i.e., 200 V). Other switches (S7, S8 and S12), however, block voltages equal to half
S3
100
the input DC source (i.e., 100 V). To sum up, unlike topologies with end side H-bridge, none of the
S5
switches required for the proposed inverter tolerate
maximum output voltage (i.e., 400 V).
0
200

VS7 &VVS11
& VS5
S3

200

100

S11
S3

S7

100

S5

0
0
200
0.96

0.97

0.98

0.99

1

VS7 & VS11

Time (sec)
S11

S

7
Figure9.
9.Voltages
Voltages
across
Figure
across the
theswitches.
switches.

100

0
0.96

0.97

0.98

0.99

Time (sec)

Figure 9. Voltages across the switches.

1

Energies 2019, 12, x FOR PEER REVIEW

12 of 15

Furthermore, the effect of different modulation indexes and switching frequencies on the
operation of the proposed inverter is shown in Figure 10. It is observed that the inverter output
Energies 2019,
207 THD at higher modulation index (and higher switching frequency). Moreover,
12 of
15
voltage
has12,
lower
the
fundamental component of output voltage is decreased at lower modulation index.
400

0
-200

0.98

0.99

Fundamental (50Hz) = 399.5
THD= 13.79%

8
6
4
2
0

0

1000

2000

3000

4000
5000
6000
Frequency (Hz)

7000

400

9000

0.97

0.98

0.99

Fundamental (50Hz) = 399.9
THD= 13.64%

8
6
4
2
0

10000

0

1000

2000

3000

4000
5000
6000
Frequency (Hz)

7000

400

8000

9000

10000

Ma= 1
fsw= 2 kHz

200

0

1

10

VLoad (V)

VLoad (V)

8000

Ma= 0.8
fsw= 4 kHz

200

0
-200

-200

0.97

0.98

0.99

1

Fundamental (50Hz) = 319.8
THD= 17.29%

10

5

0

0

1000

2000

3000

4000
5000
6000
Frequency (Hz)

7000

400

8000

9000

0.97

0.98

0.99

Fundamental (50Hz) = 399.4
THD= 13.75%

8
6
4
2
0

0

1000

2000

3000

4000
5000
6000
Frequency (Hz)

7000

400

VLoad (V)

8000

9000

10000

M a= 1
fsw= 1 kHz

200

0

1

10

10000

Ma= 0.7
fsw= 4 kHz

200

0
-200

-200

0.97

0.98

15

0.99

1

Fundamental (50Hz) = 280
THD= 21.38%

10
5

0

1000

2000

3000

4000
5000
6000
Frequency (Hz)

(a)

7000

8000

9000

-400
0.96

Mag (% of Fundamental)

-400
0.96

0

-400
0.96

Mag (% of Fundamental)

-400
0.96

Mag (% of Fundamental)

-400
0.96

1

Mag (% of Fundamental)

Mag (% of Fundamental)

0.97

10

VLoad (V)

0
-200

-400
0.96

Mag (% of Fundamental)

Ma= 1
fsw= 7 kHz

200
VLoad (V)

VLoad (V)

400

Ma= 1
fsw= 4 kHz

200

10000

0.97

0.98

10

0.99

1

Fundamental (50Hz) = 400
THD= 14.05%

8
6
4
2
0

0

1000

2000

3000

4000
5000
6000
Frequency (Hz)

7000

8000

9000

10000

(b)

Figure10.
10.The
Theeffect
effectof
of(a)
(a)modulation
modulationindex
indexon
onthe
theVVLoad
Load, (b) switching frequency on the VLoad
..
Figure
Load

performance
of the
model,model,
a low-power
prototype
of the proposed
To validate
validatethe
thehigh
high
performance
of proposed
the proposed
a low-power
prototype
of the
inverter has
been implemented
and tested. Accordingly,
Texas Instruments
(TMS320F28335)
proposed
inverter
has been implemented
and tested. aAccordingly,
a Texas
Instruments
fixed-point DSP control
boardDSP
generated
pulses
for employed
switches
500 switches
V/20 A).
(TMS320F28335)
fixed-point
controlgate
board
generated
gate pulses
for(IRFP460
employed
Moreover,500
theV/
value
of capacitances
and
inputofDC
source are and
selected
at DC
2300source
µF andare
140
V, respectively.
(IRFP460
20 A).
Moreover, the
value
capacitances
input
selected
at 2300
Figure
illustrates
the results obtained
the hardware
of the
proposed
inverter
µF
and11 140
V, respectively.
Figure from
11 illustrates
the implementation
results obtained
from
the hardware
model under steady-state
and transient
operating
conditions.
These figures and
fully transient
confirm the
flawless
implementation
of the proposed
inverter
model
under steady-state
operating
performance
of thefigures
proposed
conditions.
These
fullyinverter.
confirm the flawless performance of the proposed inverter.

Energies
2019,2019,
12, x12,
FOR
Energies
207 PEER REVIEW

13 of 15
13 of 15

VLoad

ILoad
ZLoad1=50 Ω + 100 mH

(a)

VLoad

Load reduction

ILoad

ZLoad2=ZLoad1 || 75 Ω + 100 mH

(b)
Figure
11. 11.
Output
voltage/current
constantload;
load;(b)(b)
step
change
in the
Figure
Output
voltage/currentunder,
under, (a) constant
step
change
in the
load.load.

6. Conclusions

6. Conclusions

Herein, the operating principle of a new 9 L inverter has been discussed and confirmed

Herein, the operating principle of a new 9 L inverter has been discussed and confirmed
experimentally. The comparative analysis depicted that the presented topology not only reduces the
experimentally.
The comparativelinks
analysis
depicted
that thea presented
reduces the
number of semiconductors/DC
required
for generating
9 L voltage topology
waveform,not
but only
also employs
number
semiconductors/DC
linkslead
required
generating
a cost
9 Lreduction
voltage of
waveform,
but also
IGBTsofwith
lower PIV. These merits
to a highfor
compactness
and
the conversion
employs
IGBTs
with
lower
PIV.
These
merits
lead
to
a
high
compactness
and
cost
reduction
of the
system. Due to the intrinsic self-voltage balancing ability, there is no need for complex modulation
conversion
system.
Due to
the intrinsic
balancing ability,
there is no the
need
for complex
methods.
Thereupon,
it enjoys
simple self-voltage
control and implementation.
Furthermore,
theoretical
efficiencymethods.
demonstrated
that the presented
has and
higher
efficiency by increasing
output the
modulation
Thereupon,
it enjoysconfiguration
simple control
implementation.
Furthermore,
power
(up
to
2000
W).
Eventually,
the
feasibility
and
effectiveness
of
the
proposed
model
was
verified
theoretical efficiency demonstrated that the presented configuration has higher efficiency by
by the simulation
and experimental
results.
increasing
output power
(up to 2000 W).
Eventually, the feasibility and effectiveness of the proposed
model
wasContributions:
verified by the
and experimental
results.
Author
All simulation
authors contributed
equally to this work
and all authors have read and approved the
final manuscript.

Author
Contributions:
Allreceived
authorsno
contributed
equally to this work and all authors have read and approved the
Funding:
This research
external funding.
final manuscript.
Conflicts of Interest: The authors declare no conflicts of interest.

Funding: This research received no external funding.
Conflicts of Interest: The authors declare no conflicts of interest.

Energies 2019, 12, 207

14 of 15

Nomenclature
MLIs
CHB
NPC
FC
TSV
PIV
PWM
DSP
VIN and IIN
VLoad and ILoad
Vt
Vref
VS and IS
∆Vripple
∆QC
N
M
At and ft
Aref and fref
PC
PS
PR
PS, on and PS, off
Pout
RS and RD
RC
Req
R and L
ton and toff
fS
Tj
Tc
Ts
Ta
Zth
Zc
Zs

Multilevel inverters
Cascaded H-bridge
Neutral point clamped
Flying capacitor
Total standing voltage (V)
Peak inverse voltage (V)
Pulse width modulation
Digital signal processor
Input voltage (V) and current (A) of the inverter
Maximum load voltage (V) and current (A)
Triangular carrier of the PWM modulation
Reference waveform of the PWM modulation
Voltage (V) and current (A) of the switch S
Voltage ripple across each capacitor (V)
Maximum discharging value of the capacitor C
Number of power switches with the same PIV
Number of cascaded modules
Amplitude and frequency of the triangular carriers (Vt )
Amplitude and frequency of the reference waveform (Vref )
Conduction loss (W)
Switching loss (W)
Power loss caused by capacitor voltage ripple (W)
Turn-on and turn-off power loss of the switch S (W)
Inverter output power (W)
ON-state resistance of the switch S and its parallel diode (Ω)
Capacitor internal resistance (Ω)
Equivalent value of the parasitic resistance in each voltage level (Ω)
Resistance (Ω) and inductance (H) of the load
Rise and fall times of the switch S (s)
Switching frequency (Hz)
Semiconductor junction temperature (◦ C)
Semiconductor case temperature (◦ C)
Heat sink temperature (◦ C)
Ambient temperature (◦ C)
Thermal impedance between junction and case of the semiconductor
Thermal impedance between semiconductor case and its heat sink
Thermal impedance between heat sink and ambient

References
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4.
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