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Universidade de Aveiro Departamento de Eletrónica, Telecomunicações e
Informática
2016

PURNACHAND
NALLURI

ALGORITMO DE ESTIMAÇÃO DE MOVIMENTO E
SUA ARQUITETURA DE HARDWARE PARA HEVC

A FAST MOTION ESTIMATION ALGORITHM AND
ITS VLSI ARCHITECTURE FOR HIGH EFFICIENCY
VIDEO CODING

Universidade de Aveiro Departamento de Eletrónica, Telecomunicações e
Informática
2016

PURNACHAND
NALLURI

ALGORITMO DE ESTIMAÇÃO DE MOVIMENTO E
SUA ARQUITETURA DE HARDWARE PARA HEVC

A FAST MOTION ESTIMATION ALGORITHM AND ITS
VLSI ARCHITECTURE FOR HIGH EFFICIENCY VIDEO
CODING
Tese apresentada à Universidade de Aveiro para cumprimento dos requisitos
necessários à obtenção do grau de Doutor em Engenharia Eletrotécnica,
realizada sob a orientação científica do Doutor António José Nunes Navarro
Rodrigues, Professor Auxiliar do Departamento de Eletrónica, Telecomunicações e Informática da Universidade de Aveiro e do Doutor Luis Filipe
Mesquita Nero Moreira Alves, Professor Auxiliar do Departamento de
Eletrónica, Telecomunicações e Informática da Universidade de Aveiro.

This PhD thesis was supported by FCT
(Fundação para a Ciência e a
Tecnologia), Portugal. Grant ref.
:SFRH/BD/73266/2010

dedicated to my family
my brother late Govind Nalluri
my dad and mom
and my wife

O Júri
Presidente:

Doutor Fernando Manuel dos Santos Ramos, Professor Catedrático,
Universidade de Aveiro

Vogais:

Doutor Luciano Volcan Agostini, Pró-Reitor de Pesquisa e Pós-Graduação,
Universidade Federal de Pelotas, Brasil
Doutor Marco Mattavelli, Maître D’enseignement et de Recherche, École
Polytechnique Fédérale de Lausanne, Suiça
Doutor Leonel Augusto Pires Seabra de Sousa, Professor Catedrático, Instituto
Superior Técnico, Universidade de Lisboa
Doutor Dinis Gomes de Magalhães dos Santos, Professor Catedrático,
Universidade de Aveiro
Doutor António José Nunes Navarro Rodrigues, Professor Auxiliar,
Universidade de Aveiro (supervisor/orientador)

agradecimentos

The research work for this thesis was carried at Institudo de Telecomunicações (IT) and
Departamento de Electrónica, Telecomunicações e Informática (DETI), Universidade
de Aveiro, Campus Universitário de Santiago, Aveiro, Portugal, during the years 20102015.
I would like to express my gratitude to my supervisors Prof. Luis Nero Alves and Prof.
Antonio Navarro for their guidance, motivation and every possible effort to carry out
my research work. Prof. Luis Nero taught me how to approach towards a problem
(especially in VLSI circuits and systems) in research work, and motivated at many
points. Prof. Navarro’s experience in video coding helped how to solve the critical
problems without which this thesis could not have been accomplished.
I would like to thank Prof. Manuel Almeida Valente for his great help and support
given to me in the initial days of my arrival to Portugal, and because of whom I came to
know about Aveiro and FCT scholarship.
I would like to thank all my colleagues in CSI lab of IT, Aveiro for their technical
support and friendship, Nuno Lourenço, Domingos Terra, Miguel Bergano, Nelson
Silva and Mónica Figueiredo all made the lab a comfortable place to work. I would also
like to express my thankfulness to IT administrative, HR and security staff for their
cooperation throughout my stay in IT.
I would like to thank my family, my wife Sirisha and my parents (dad Prof. Dr. N.
Veeraiah and mom N.V. Kumari) for their wonderful support and love that helped me
survive in difficult times. I would also like to thank my uncles Dr. V. Ravikumar, Dr.
G. Sahaya Bhaskaran, Dr. Y. Gandhi, Dr. K.S.V. Sudhakar, Dr. G. Nagaraju and to my
cousin Valluri Ravikumar for their support throughout my PhD period.
I would like to express my gratefulness to my loving brother late Govind Nalluri,
whose very thoughts are foundation to my conscience.
Finally, I would like to thank and acknowledge my funding agency FCT (Fundação
para a Ciência e a Tecnologia). This research work was supported by FCT grant
reference SFRH/BD/73266/2010.

palavras-chave

Codificação de vídeo, Norma HEVC, Estimação de movimento, Arquitetura de
hardware, FPGA.

resumo

A codificação de vídeo tem sido usada em aplicações tais como, vídeovigilância, vídeo-conferência, video streaming e armazenamento de vídeo.
Numa norma de codificação de vídeo, diversos algoritmos são combinados
para comprimir o vídeo. Contudo, um desses algoritmos, a estimação de
movimento é a tarefa mais complexa. Por isso, é necessário implementar esta
tarefa em tempo real usando arquiteturas de hardware apropriadas. Esta tese
propõe um algoritmo de estimação de movimento rápido bem como a sua
implementação em tempo real. Os resultados mostram que o algoritmo e a
arquitetura de hardware propostos têm melhor desempenho que os existentes.
A arquitetura proposta opera a uma frequência máxima de 241.6 MHz e é
capaz de processar imagens de resolução 1080p@60Hz, com todos os
tamanhos de blocos especificados na norma HEVC, bem como um domínio de
pesquisa de vetores de movimento até ±64 pixels.

keywords

Video Coding, HEVC standard, Motion Estimation, VLSI Architecture, FPGA.

abstract

Video coding has been used in applications like video surveillance, video
conferencing, video streaming, video broadcasting and video storage. In a
typical video coding standard, many algorithms are combined to compress a
video. However, one of those algorithms, the motion estimation is the most
complex task. Hence, it is necessary to implement this task in real time by
using appropriate VLSI architectures. This thesis proposes a new fast motion
estimation algorithm and its implementation in real time. The results show that
the proposed algorithm and its motion estimation hardware architecture out
performs the state of the art. The proposed architecture operates at a
maximum operating frequency of 241.6 MHz and is able to process
1080p@60Hz with all possible variables block sizes specified in HEVC
standard as well as with motion vector search range of up to ±64 pixels.

Table of Contents

Table of Contents
TABLE OF CONTENTS .............................................................................. I
LIST OF FIGURES .................................................................................. VII
LIST OF ACRONYMS ................................................................................ X
1 INTRODUCTION ..................................................................................... 1
1.1 PROBLEM DEFINITION AND MOTIVATION ............................................... 1
1.1.1 The Need of Video Compression ........................................................................... 1
1.1.2 Block-based Video Encoder System ...................................................................... 3
1.1.3 The Motion Estimation Problem ............................................................................ 4
1.1.4 The Demand for Video Core Complexity .............................................................. 5

1.2 OBJECTIVES OF THESIS................................................................................... 6
1.3 SUMMARY OF ORIGINAL CONTRIBUTIONS ............................................. 7
1.4 SUMMARY OF THESIS....................................................................................... 8

2 FUNDAMENTALS OF DIGITAL VIDEO CODING AND MOTION
ESTIMATION............................................................................................... 9
2.1 INTRODUCTION .................................................................................................. 9
2.2 DIGITAL VIDEO CODING TERMINOLOGY ................................................. 9
Block Based Video Coding ................................................................................... 9
Group of Pictures (GOP) ....................................................................................... 9
Pictures, Frames and Fields ................................................................................. 10
Slices and Coding Blocks .................................................................................... 11
Pixel Color space and Sampling Techniques ........................................................ 12
Video Formats..................................................................................................... 13
Video Quality Measurement ................................................................................ 13

i

List of Figures

Video Bitrate ....................................................................................................... 14
Rate Distortion Performance for Video Encoder .................................................. 16
Bjontegaard Delta Metrics for RD Performance Measurement ............................. 16

2.3 TYPES OF REDUNDANCIES IN DIGITAL VIDEO ..................................... 17
2.4 DIGITAL VIDEO COMPRESSION TECHNIQUES ...................................... 19
Intra Frame Coding ............................................................................................. 19
Inter Frame Coding ............................................................................................. 19
Transform Coding and Quantization .................................................................... 20
Entropy Coding ................................................................................................... 20

2.5 DIGITAL VIDEO CODING STANDARDS...................................................... 21
History of video coding standards........................................................................ 21
ITU/VCEG standards .......................................................................................... 22
ISO/MPEG Standards.......................................................................................... 24
Other standards ................................................................................................... 25

2.6 H.264/AVC CODING STRUCTURE ................................................................. 26
2.7 HEVC CODING STRUCTURE ......................................................................... 26
2.8 REFERENCE SOFTWARES FOR VIDEO CODING STANDARDS ........... 27
H.264/AVC Reference Software JM .................................................................... 27
HEVC Reference Software HM........................................................................... 27
Various Configurations in HM ............................................................................ 28
Reference Test Sequences for HM ....................................................................... 30

2.9 BLOCK DIAGRAM OF HEVC ENCODER .................................................... 31
2.10MOTION ESTIMATION FEATURES ............................................................. 36
Motion Estimation Objective ............................................................................... 36
Variable Block Size Motion Estimation ............................................................... 37
Multiple Reference Frames for Motion Estimation .............................................. 39

ii


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