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Title: Programming Environments Manual for 32-Bit Implementations of the PowerPC™ Architecture
Author: Freescale Semiconductor

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Programming Environments Manual
for 32-Bit Implementations of the
PowerPC™ Architecture

MPCFPE32B
Rev. 3, 9/2005

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© Freescale Semiconductor, Inc., 2005. All rights reserved.

Document Number: MPCFPE32B
Rev. 3, 9/2005

Overview

1

Register Set

2

Operand Conventions

3

Addressing Modes

4

Cache

5

Exceptions

6

Memory Management Unit

7

Instruction Set

8

Instruction Set Listings

A

Multiple-Precision Shifts

B

Floating-Point Models

C

Synchronization Programming Examples

D

Simplified Mnemonics

E

PEM Revision History

F

Glossary

GLO

Index

IND

1

Overview

2

Register Set

3

Operand Conventions

4

Addressing Modes

5

Cache

6

Exceptions

7

Memory Management Unit

8

Instruction Set

A

Instruction Set Listings

B

Multiple-Precision Shifts

C

Floating-Point Models

D

Synchronization Programming Examples

E

Simplified Mnemonics

F

PEM Revision History

GLO

Glossary

IND

Index

Contents
Paragraph
Number

Title

Page
Number

Chapter 1
Overview
1.1
1.1.1
1.1.2
1.1.3
1.2
1.2.1
1.2.2
1.2.2.1
1.2.2.2
1.2.2.3
1.2.3
1.2.3.1
1.2.3.2
1.2.4
1.2.5
1.2.6

PowerPC Architecture Overview..................................................................................... 1-2
The Levels of the PowerPC Architecture .................................................................... 1-3
Latitude within the Levels of the Architecture ............................................................ 1-4
Features Not Defined by the PowerPC Architecture ................................................... 1-4
The Architectural Models ................................................................................................ 1-5
Registers and Programming Model ............................................................................. 1-5
Operand Conventions .................................................................................................. 1-7
Byte Ordering .......................................................................................................... 1-7
Data Organization in Memory and Data Transfers.................................................. 1-8
Floating-Point Conventions ..................................................................................... 1-8
Instruction Set and Addressing Modes ........................................................................ 1-8
Instruction Set.......................................................................................................... 1-8
Calculating Effective Addresses............................................................................ 1-10
Cache Model .............................................................................................................. 1-10
Interrupt Model .......................................................................................................... 1-10
Memory Management Model (MMU)....................................................................... 1-11
Chapter 2
Register Set

2.1
2.1.1
2.1.2
2.1.3
2.1.3.1
2.1.3.2
2.1.3.3
2.1.4
2.1.5
2.1.6
2.1.7
2.2
2.2.1
2.2.2
2.3
2.3.1

UISA Register Set............................................................................................................ 2-1
General-Purpose Registers (GPRs).............................................................................. 2-3
Floating-Point Registers (FPRs) .................................................................................. 2-3
Condition Register (CR) .............................................................................................. 2-5
Condition Register CR0 Field Definition ................................................................ 2-5
Condition Register CR1 Field Definition ................................................................ 2-6
Condition Register CRn Field—Compare Instruction ............................................ 2-6
Floating-Point Status and Control Register (FPSCR).................................................. 2-6
XER Register (XER) ................................................................................................... 2-9
Link Register (LR)..................................................................................................... 2-10
Count Register (CTR)................................................................................................ 2-11
VEA Register Set—Time Base...................................................................................... 2-12
Reading the Time Base .............................................................................................. 2-14
Computing Time of Day from the Time Base ........................................................... 2-15
OEA Register Set........................................................................................................... 2-15
Machine State Register (MSR) .................................................................................. 2-18
Programming Environments Manual for 32-Bit Implementations of the PowerPC Architecture, Rev. 3

Freescale Semiconductor

v

Contents
Paragraph
Number
2.3.2
2.3.3
2.3.4
2.3.5
2.3.6
2.3.7
2.3.8
2.3.9
2.3.10
2.3.11
2.3.12
2.3.12.1
2.3.13
2.3.13.1
2.3.13.2
2.3.14
2.3.15
2.3.16
2.3.17

Title

Page
Number

Processor Version Register (PVR)............................................................................. 2-21
BAT Registers ............................................................................................................ 2-21
SDR1.......................................................................................................................... 2-24
Segment Registers...................................................................................................... 2-25
Data Address Register (DAR) ................................................................................... 2-26
SPRG0–SPRG3 ......................................................................................................... 2-26
DSISR ........................................................................................................................ 2-27
Machine Status Save/Restore Register 0 (SRR0) ...................................................... 2-27
Machine Status Save/Restore Register 1 (SRR1) ...................................................... 2-28
Floating-Point Exception Cause Register (FPECR) .................................................. 2-28
Time Base Facility (TB)—OEA ................................................................................ 2-29
Writing to the Time Base ....................................................................................... 2-29
Decrementer Register (DEC)..................................................................................... 2-29
Decrementer Operation.......................................................................................... 2-30
Writing and Reading the DEC ............................................................................... 2-30
Data Address Breakpoint Register (DABR ) ............................................................. 2-30
External Access Register (EAR)................................................................................ 2-32
Processor Identification Register (PIR) ..................................................................... 2-32
Synchronization Requirements for Special Registers and for Lookaside Buffers..... 2-33
Chapter 3
Operand Conventions

3.1
3.1.1
3.1.2
3.1.3
3.1.3.1
3.1.3.2
3.1.4
3.1.4.1
3.1.4.2
3.1.4.3
3.1.4.4
3.1.4.5
3.2
3.2.1
3.2.2
3.3
3.3.1
3.3.1.1

Data Organization in Memory and Data Transfers .......................................................... 3-1
Aligned and Misaligned Accesses ............................................................................... 3-1
Byte Ordering .............................................................................................................. 3-2
Structure Mapping Examples....................................................................................... 3-2
Big-Endian Mapping ............................................................................................... 3-2
Little-Endian Mapping............................................................................................. 3-3
Byte Ordering in PowerPC Architecture ..................................................................... 3-4
Aligned Scalars in Little-Endian Mode ................................................................... 3-4
Misaligned Scalars in Little-Endian Mode .............................................................. 3-6
Nonscalars................................................................................................................ 3-7
Instruction Addressing in Little-Endian Mode ........................................................ 3-7
Input/Output Data Transfer Addressing in Little-Endian Mode.............................. 3-8
Operand Placement and Performance—VEA.................................................................. 3-8
Summary of Performance Effects................................................................................ 3-8
Instruction Restart...................................................................................................... 3-10
Floating-Point Execution Models—UISA..................................................................... 3-10
Floating-Point Data Format ....................................................................................... 3-11
Value Representation ............................................................................................. 3-12
Programming Environments Manual for 32-Bit Implementations of the PowerPC Architecture, Rev. 3

vi

Freescale Semiconductor

Contents
Paragraph
Number
3.3.1.2
3.3.1.3
3.3.1.4
3.3.1.5
3.3.1.6
3.3.1.7
3.3.2
3.3.3
3.3.4
3.3.5
3.3.6
3.3.6.1
3.3.6.1.1
3.3.6.1.2
3.3.6.2
3.3.6.2.1
3.3.6.2.2
3.3.6.2.3

Title

Page
Number

Binary Floating-Point Numbers............................................................................. 3-13
Normalized Numbers (±NORM) ........................................................................... 3-14
Zero Values (±0) .................................................................................................... 3-14
Denormalized Numbers (±DENORM).................................................................. 3-14
Infinities (±∞) ........................................................................................................ 3-15
Not a Numbers (NaNs) .......................................................................................... 3-15
Sign of Result............................................................................................................. 3-16
Normalization and Denormalization.......................................................................... 3-17
Data Handling and Precision ..................................................................................... 3-17
Rounding.................................................................................................................... 3-19
Floating-Point Program Exceptions........................................................................... 3-21
Invalid Operation and Zero Divide Exception Conditions .................................... 3-27
Invalid Operation Exception Condition............................................................. 3-29
Zero Divide Exception Condition...................................................................... 3-30
Overflow, Underflow, and Inexact Exception Conditions..................................... 3-31
Overflow Exception Condition.......................................................................... 3-33
Underflow Exception Condition........................................................................ 3-34
Inexact Exception Condition ............................................................................. 3-35
Chapter 4
Addressing Modes and Instruction Set Summary

4.1
4.1.1
4.1.2
4.1.2.1
4.1.2.2
4.1.2.2.1
4.1.2.2.2
4.1.2.2.3
4.1.2.3
4.1.2.4
4.1.3
4.1.3.1
4.1.3.2
4.1.4
4.1.4.1
4.1.4.2
4.1.5
4.1.6
4.2

Conventions ..................................................................................................................... 4-2
Sequential Execution Model........................................................................................ 4-2
Classes of Instructions ................................................................................................. 4-2
Definition of Boundedly Undefined ........................................................................ 4-3
Defined Instruction Class ........................................................................................ 4-3
Preferred Instruction Forms................................................................................. 4-3
Invalid Instruction Forms .................................................................................... 4-3
Optional Instructions ........................................................................................... 4-4
Illegal Instruction Class ........................................................................................... 4-4
Reserved Instructions............................................................................................... 4-5
Memory Addressing .................................................................................................... 4-5
Memory Operands ................................................................................................... 4-5
Effective Address Calculation ................................................................................. 4-6
Synchronizing Instructions .......................................................................................... 4-6
Context Synchronizing Instructions ........................................................................ 4-7
Execution Synchronizing Instructions ..................................................................... 4-7
Interrupt Summary ....................................................................................................... 4-7
Recommended Simplified Mnemonics........................................................................ 4-8
UISA Instructions ............................................................................................................ 4-8

Programming Environments Manual for 32-Bit Implementations of the PowerPC Architecture, Rev. 3
Freescale Semiconductor

vii

Contents
Paragraph
Number
4.2.1
4.2.1.1
4.2.1.2
4.2.1.3
4.2.1.4
4.2.1.4.1
4.2.1.4.2
4.2.2
4.2.2.1
4.2.2.2
4.2.2.3
4.2.2.4
4.2.2.5
4.2.2.6
4.2.3
4.2.3.1
4.2.3.1.1
4.2.3.1.2
4.2.3.1.3
4.2.3.2
4.2.3.3
4.2.3.4
4.2.3.5
4.2.3.6
4.2.3.7
4.2.3.7.1
4.2.3.7.2
4.2.3.8
4.2.3.9
4.2.4
4.2.4.1
4.2.4.1.1
4.2.4.1.2
4.2.4.1.3
4.2.4.1.4
4.2.4.1.5
4.2.4.1.6

Title

Page
Number

Integer Instructions ...................................................................................................... 4-8
Integer Arithmetic Instructions................................................................................ 4-9
Integer Compare Instructions ................................................................................ 4-12
Integer Logical Instructions................................................................................... 4-13
Integer Rotate and Shift Instructions ..................................................................... 4-15
Integer Rotate Instructions................................................................................. 4-15
Integer Shift Instructions ................................................................................... 4-16
Floating-Point Instructions ........................................................................................ 4-17
Floating-Point Arithmetic Instructions .................................................................. 4-18
Floating-Point Multiply-Add Instructions ............................................................. 4-20
Floating-Point Rounding and Conversion Instructions ......................................... 4-21
Floating-Point Compare Instructions..................................................................... 4-22
Floating-Point Status and Control Register Instructions ....................................... 4-22
Floating-Point Move Instructions .......................................................................... 4-23
Load and Store Instructions ....................................................................................... 4-24
Integer Load and Store Address Generation.......................................................... 4-24
Register Indirect with Immediate Index Addressing
for Integer Loads and Stores.......................................................................... 4-25
Register Indirect with Index Addressing for Integer Loads and Stores............. 4-25
Register Indirect Addressing for Integer Loads and Stores............................... 4-26
Integer Load Instructions....................................................................................... 4-27
Integer Store Instructions....................................................................................... 4-29
Integer Load and Store with Byte-Reverse Instructions........................................ 4-30
Integer Load and Store Multiple Instructions ........................................................ 4-31
Integer Load and Store String Instructions ............................................................ 4-31
Floating-Point Load and Store Address Generation .............................................. 4-32
Register Indirect with Immediate Index Addressing for Floating-Point
Loads and Stores............................................................................................ 4-32
Register Indirect with Index Addressing for Floating-Point
Loads and Stores............................................................................................ 4-33
Floating-Point Load Instructions ........................................................................... 4-34
Floating-Point Store Instructions ........................................................................... 4-35
Branch and Flow Control Instructions....................................................................... 4-36
Branch Instruction Address Calculation................................................................ 4-37
Branch Relative Addressing Mode.................................................................... 4-37
Branch Conditional to Relative Addressing Mode............................................ 4-38
Branch to Absolute Addressing Mode............................................................... 4-39
Branch Conditional to Absolute Addressing Mode........................................... 4-40
Branch Conditional to Link Register Addressing Mode ................................... 4-41
Branch Conditional to Count Register Addressing Mode ................................. 4-41

Programming Environments Manual for 32-Bit Implementations of the PowerPC Architecture, Rev. 3
viii

Freescale Semiconductor

Contents
Paragraph
Number
4.2.4.2
4.2.4.3
4.2.4.4
4.2.4.5
4.2.4.6
4.2.4.7
4.2.5
4.2.5.1
4.2.5.2
4.2.6
4.3
4.3.1
4.3.2
4.3.3
4.3.3.1
4.3.4
4.4
4.4.1
4.4.2
4.4.2.1
4.4.2.2
4.4.3
4.4.3.1
4.4.3.2
4.4.3.3

Title

Page
Number

Conditional Branch Control................................................................................... 4-42
Branch Instructions................................................................................................ 4-45
Simplified Mnemonics for Branch Processor Instructions.................................... 4-45
Condition Register Logical Instructions................................................................ 4-46
Trap Instructions .................................................................................................... 4-46
System Linkage Instruction—UISA...................................................................... 4-47
Processor Control Instructions—UISA ..................................................................... 4-47
Move to/from Condition Register Instructions...................................................... 4-47
Move to/from Special-Purpose Register Instructions (UISA)............................... 4-47
Memory Synchronization Instructions—UISA ......................................................... 4-48
VEA Instructions ........................................................................................................... 4-49
Processor Control Instructions—VEA....................................................................... 4-50
Memory Synchronization Instructions—VEA .......................................................... 4-51
Memory Control Instructions—VEA ........................................................................ 4-51
User-Level Cache Instructions—VEA .................................................................. 4-52
External Control Instructions (Optional) ................................................................... 4-54
OEA Instructions ........................................................................................................... 4-55
System Linkage Instructions—OEA ......................................................................... 4-55
Processor Control Instructions—OEA....................................................................... 4-56
Move to/from Machine State Register Instructions............................................... 4-56
Move to/from Special-Purpose Register Instructions (OEA) ................................ 4-56
Memory Control Instructions—OEA ........................................................................ 4-57
Supervisor-Level Cache Management Instruction ................................................ 4-57
Segment Register Manipulation Instructions......................................................... 4-58
Translation Lookaside Buffer Management Instructions ...................................... 4-59
Chapter 5
Cache Model and Memory Coherency

5.1
5.2
5.2.1
5.2.1.1
5.2.1.2
5.2.2
5.2.3
5.2.4
5.2.4.1
5.2.4.1.1
5.2.4.1.2
5.2.4.1.3

Overview.......................................................................................................................... 5-1
The Virtual Environment ................................................................................................. 5-1
Memory Access Ordering............................................................................................ 5-2
Enforce In-Order Execution of I/O Instruction (eieio) ............................................ 5-2
Synchronize Instruction ........................................................................................... 5-3
Atomicity ..................................................................................................................... 5-3
Cache Model ................................................................................................................ 5-4
Memory Coherency ..................................................................................................... 5-4
Memory/Cache Access Modes ................................................................................ 5-4
Pages Designated as Write-Through.................................................................... 5-5
Pages Designated as Caching-Inhibited .............................................................. 5-5
Pages Designated as Memory Coherency Required............................................ 5-5

Programming Environments Manual for 32-Bit Implementations of the PowerPC Architecture, Rev. 3
Freescale Semiconductor

ix


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